Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 264
2009-2011 Microchip Technology Inc.
20.3
Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the ECCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the ECCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
20.3.1
ECCP PIN CONFIGURATION
Users must configure the ECCPx pin as an output by
clearing the appropriate TRIS bit.
clearing the appropriate TRIS bit.
20.3.2
TIMER1/2/3/4/6/8/10/12 MODE
SELECTION
SELECTION
Timer1 2, 3, 4, 6, 8, 10 or 12 must be running in Timer
mode or Synchronized Counter mode if the ECCP
module is using the compare feature. In Asynchronous
Counter mode, the compare operation will not work
reliably.
mode or Synchronized Counter mode if the ECCP
module is using the compare feature. In Asynchronous
Counter mode, the compare operation will not work
reliably.
20.3.3
SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the ECCPx pin is not affected;
only the CCPxIF interrupt flag is affected.
(CCPxM<3:0> = 1010), the ECCPx pin is not affected;
only the CCPxIF interrupt flag is affected.
20.3.4
SPECIAL EVENT TRIGGER
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPRx registers to
serve as a programmable Period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPRx registers to
serve as a programmable Period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
FIGURE 20-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Note:
Clearing the CCPxCON register will force
the ECCPx compare output latch
(depending on device configuration) to the
default low level. This is not the PORTx
I/O data latch.
the ECCPx compare output latch
(depending on device configuration) to the
default low level. This is not the PORTx
I/O data latch.
TMR1H
TMR1L
TMR3H
TMR3L
CCPR1H
CCPR1L
Comparator
Set CCP1IF
1
0
Q
S
R
Output
Logic
ECCP1 Pin
TRIS
CCP1CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset, A/D Trigger)
Compare
Match
C1TSEL0
C1TSEL1
C1TSEL2
Special Event Trigger