Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet

 2009-2011 Microchip Technology Inc.

DS39960D-page 145

  

 

R/W-1

R/W-1

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

 INT2 External Interrupt Priority bit

1

  = High  priority 

0

 = Low priority 

bit 6

 INT1 External Interrupt Priority bit

1

  = High  priority 

0

 = Low priority 

bit 5

 INT3 External Interrupt Enable bit

1

 = Enables the INT3 external interrupt 

0

 = Disables the INT3 external interrupt 

bit 4

 INT2 External Interrupt Enable bit

1

 = Enables the INT2 external interrupt 

0

 = Disables the INT2 external interrupt 

bit 3

 INT1 External Interrupt Enable bit 

1

 = Enables the INT1 external interrupt 

0

 = Disables the INT1 external interrupt 

bit 2

 INT3 External Interrupt Flag bit

1

= The INT3 external interrupt occurred (must be cleared in software) 

0

 = The INT3 external interrupt did not occur

bit 1

 INT2 External Interrupt Flag bit

1

= The INT2 external interrupt occurred (must be cleared in software) 

0

 = The INT2 external interrupt did not occur

bit 0

 INT1 External Interrupt Flag bit 

1

 = The INT1 external interrupt occurred (must be cleared in software) 

0

 = The INT1 external interrupt did not occur 

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.