Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 163
PIC18F87K22 FAMILY
11.6
INTx Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge. If
that bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit
(INTxIF) must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit (GIE) is set, the processor will branch to the interrupt
vector following wake-up.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the Interrupt
Priority bits, INT1IP (INTCON3<6>), INT2IP
(INTCON3<7>) and INT3IP (INTCON2<1>).
There is no priority bit associated with INT0. It is always
a high-priority interrupt source.
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge. If
that bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit
(INTxIF) must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit (GIE) is set, the processor will branch to the interrupt
vector following wake-up.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the Interrupt
Priority bits, INT1IP (INTCON3<6>), INT2IP
(INTCON3<7>) and INT3IP (INTCON2<1>).
There is no priority bit associated with INT0. It is always
a high-priority interrupt source.
11.7
TMR0 Interrupt
In 8-bit mode (the default), an overflow in the TMR0
register (FFh
register (FFh
00h) will set flag bit, TMR0IF. In 16-bit
mode, an overflow in the TMR0H:TMR0L register pair
(FFFFh
(FFFFh
0000h) will set TMR0IF.
The interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the inter-
rupt priority bit, TMR0IP (INTCON2<2>). For further
details on the Timer0 module, see Section 13.0 “Timer0
Module”
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the inter-
rupt priority bit, TMR0IP (INTCON2<2>). For further
details on the Timer0 module, see Section 13.0 “Timer0
Module”
.
11.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
11.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
If a fast return from interrupt is not used (see
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
If a fast return from interrupt is not used (see
), the user
may need to save the WREG, STATUS and BSR regis-
ters on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
may also need to be saved.
ters on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
may also need to be saved.
saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
EXAMPLE 11-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
; W_TEMP is in virtual bank
MOVFF
STATUS, STATUS_TEMP
; STATUS_TEMP located anywhere
MOVFF
BSR, BSR_TEMP
; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
; Restore BSR
MOVF
W_TEMP, W
; Restore WREG
MOVFF
STATUS_TEMP, STATUS
; Restore STATUS