Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 195
PIC18F87K22 FAMILY
13.3
Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>), which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-two increments,
are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (for example, CLRF TMR0,
MOVWF TMR0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>), which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-two increments,
are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (for example, CLRF TMR0,
MOVWF TMR0
, BSF TMR0) clear the prescaler count.
13.3.1
SWITCHING PRESCALER
ASSIGNMENT
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
control and can be changed “on-the-fly” during program
execution.
13.4
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine (ISR).
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine (ISR).
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 13-1:
REGISTERS ASSOCIATED WITH TIMER0
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0L
Timer0 Register Low Byte
TMR0H
Timer0 Register High Byte
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
T0CON
TMR0ON
T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.