Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 201
PIC18F87K22 FAMILY
14.4
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits at once to both the high and low bytes of Timer1.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler; the
prescaler is only cleared on writes to TMR1L.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits at once to both the high and low bytes of Timer1.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler; the
prescaler is only cleared on writes to TMR1L.
14.5
SOSC Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, SOSCI (input) and SOSCO (amplifier
output). It is enabled by any peripheral that requests it.
There are eight ways the SOSC can be enabled: if the
SOSC is selected as the source by any of the odd
timers, which is done by each respective SOSCEN bit
(TxCON<3>), if the SOSC is selected as the RTCC
source by the RTCOSC Configuration bit
(CONFIG3L<1>), if the SOSC is selected as the CPU
clock source by the SCS bits (OSCCON<1:0>) or if the
SOSCGO bit is set (OSCCON2<3>). The SOSCGO bit
is used to warm up the SOSC so that it is ready before
any peripheral requests it. The oscillator is a low-power
circuit, rated for 32 kHz crystals. It will continue to run
during all power-managed modes. The circuit for a typi-
cal low-power oscillator is depicted in
between pins, SOSCI (input) and SOSCO (amplifier
output). It is enabled by any peripheral that requests it.
There are eight ways the SOSC can be enabled: if the
SOSC is selected as the source by any of the odd
timers, which is done by each respective SOSCEN bit
(TxCON<3>), if the SOSC is selected as the RTCC
source by the RTCOSC Configuration bit
(CONFIG3L<1>), if the SOSC is selected as the CPU
clock source by the SCS bits (OSCCON<1:0>) or if the
SOSCGO bit is set (OSCCON2<3>). The SOSCGO bit
is used to warm up the SOSC so that it is ready before
any peripheral requests it. The oscillator is a low-power
circuit, rated for 32 kHz crystals. It will continue to run
during all power-managed modes. The circuit for a typi-
cal low-power oscillator is depicted in
.
provides the capacitor selection for the
SOSC oscillator.
The user must provide a software time delay to ensure
proper start-up of the SOSC oscillator.
The user must provide a software time delay to ensure
proper start-up of the SOSC oscillator.
FIGURE 14-2:
EXTERNAL COMPONENTS
FOR THE SOSC
LOW-POWER OSCILLATOR
FOR THE SOSC
LOW-POWER OSCILLATOR
TABLE 14-2:
CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR
THE TIMER
OSCILLATOR
(
The SOSC crystal oscillator drive level is determined
based on the SOSCSEL<1:0> (CONFIG1L<4:3>) Con-
figuration bits. The Higher Drive Level mode,
SOSCSEL<1:0> = 11, is intended to drive a wide variety
of 32.768 kHz crystals with a variety of Capacitance
Load (CL) ratings.
based on the SOSCSEL<1:0> (CONFIG1L<4:3>) Con-
figuration bits. The Higher Drive Level mode,
SOSCSEL<1:0> = 11, is intended to drive a wide variety
of 32.768 kHz crystals with a variety of Capacitance
Load (CL) ratings.
Oscillator
Type
Freq.
C1
C2
LP
32 kHz
12 pF
12 pF
Note 1:
Microchip suggests these values as a
starting point in validating the oscillator
circuit.
starting point in validating the oscillator
circuit.
2:
Higher capacitance increases the stabil-
ity of the oscillator, but also increases the
start-up time.
ity of the oscillator, but also increases the
start-up time.
3:
Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4:
Capacitor values are for design guid-
ance only. Values listed would be typical
of a CL = 10 pF rated crystal when
SOSCSEL<1:0> = 11.
ance only. Values listed would be typical
of a CL = 10 pF rated crystal when
SOSCSEL<1:0> = 11.
5:
Incorrect capacitance value may result in
a frequency not meeting the crystal
manufacturer’s tolerance specification.
a frequency not meeting the crystal
manufacturer’s tolerance specification.
Note:
See the Notes with
for additional
information about capacitor selection.
C1
C2
XTAL
SOSCI
SOSCO
32.768 kHz
12 pF
12 pF
PIC18F87K22