Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 215
PIC18F87K22 FAMILY
16.2
Timer3/5/7 Operation
Timer3, Timer5 and Timer7 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
OSC
/4). When TMRxCSx = 01, the
Timer3/5/7 clock source is the system clock (F
OSC
), and
when it is ‘10’, Timer3/5/7 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
FIGURE 16-1:
TIMER3/5/7 BLOCK DIAGRAM
TMR3H
TMR3L
T3SYNC
T3CKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
Clock Input
2
Set Flag bit
TMR3IF on
Overflow
TMR3IF on
Overflow
TMR3
(2)
TMR3ON
Note
1:
ST Buffer is high-speed type when using T3CKI.
2:
Timer3 registers increment on rising edge.
3:
Synchronization does not operate while in Sleep.
4:
The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.
T3G
SOSC
F
OSC
/4
Internal
Clock
SOSCO/SCLKI
SOSCI
1
0
T3CKI
TMR3CS<1:0>
(1)
Synchronize
(3)
det
Sleep Input
TMR3GE
0
1
00
01
10
11
From TMR4
From Comparator 1
T3GPOL
D
Q
CK
Q
0
1
T3GVAL
T3GTM
Single Pulse
Acq. Control
T3GSPM
T3GGO/T3DONE
T3GSS<1:0>
EN
OUT
(4)
10
00
01
F
OSC
Internal
Clock
From Comparator 2
Output
Match PR4
R
D
EN
Q
Q1
RD
T3GCON
Data Bus
det
Interrupt
TMR3GIF
Set
T3CLK
F
OSC
/2
Internal
Clock
D
EN
Q
T3G_IN
TMR3ON
Output
T1CON.SOSCEN
T3CON.SOSCEN
SOSCGO
SCS<1:0> = 01