Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 255
PIC18F87K22 FAMILY
19.4
PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
shows a simplified block diagram of the
ECCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
.
FIGURE 19-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
DIAGRAM
A PWM output (
) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 19-4:
PWM OUTPUT
19.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
register. The PWM period can be calculated using the
following formula:
EQUATION 19-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP4 pin is set
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP4 pin is set
(An exception: If PWM duty cycle = 0%, the CCP4
pin will not be set)
pin will not be set)
• The PWM duty cycle is latched from CCPR4L into
CCPR4H
Note:
Clearing the CCP4CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
CCPR4L
CCPR4H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCP4CON<5:4>
Clear Timer,
ECCP1 Pin and
Latch D.C.
TRISC<2>
RC2/ECCP1
Note 1:
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
2:
CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see
example. For details on all of the CCP modules and
their timer assignments, see
and
(Note 2)
(Note 2)
Note:
The Timer2 postscalers (see
) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM Period = [(PR2) + 1] • 4 • T
OSC
•
(TMR2 Prescale Value)