Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 408
2009-2011 Microchip Technology Inc.
REGISTER 28-4:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN1
WDTEN0
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6-2
WDTPS<4:0>:
Watchdog Timer Postscale Select bits
10101-11111
= Reserved
10100
= 1:1,048,576 (4,194.304s)
10011
= 1:524,288 (2,097.152s)
10010
= 1:262,144 (1,048.576s)
10001
= 1:131,072 (524.288s)
10000
= 1:65,536 (262.144s)
01111
= 1:32,768 (131.072s)
01110
= 1:16,384 (65.536s)
01101
= 1:8,192 (32.768s)
01100
= 1:4,096 (16.384s)
01011
= 1:2,048 (8.192s)
01010
= 1:1,024 (4.096s)
01001
= 1:512 (2.048s)
01000
= 1:256 (1.024s)
00111
= 1:128 (512 ms)
00110
= 1:64 (256 ms)
00101
= 1:32 (128 ms)
00100
= 1:16 (64 ms)
00011
= 1:8 (32 ms)
00010
= 1:4 (16 ms)
00001
= 1:2 (8 ms)
00000
= 1:1 (4 ms)
bit 1-0
WDTEN<1:0>:
Watchdog Timer Enable bits
11
= WDT is enabled in hardware; SWDTEN bit is disabled
10
= WDT is controlled by the SWDTEN bit setting
01
= WDT is enabled only while the device is active and disabled in Sleep mode; SWDTEN bit is
disabled
00
= WDT is disabled in hardware; SWDTEN bit is disabled