Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2011 Microchip Technology Inc.
DS39960D-page 505
PIC18F87K22 FAMILY
FIGURE 31-5:
CLKO AND I/O TIMING
TABLE 31-9:
CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
T
OS
H2
CK
L OSC1
to CLKO
—
75
200
ns
11
T
OS
H2
CK
H OSC1
to CLKO
—
75
200
ns
12
T
CK
R
CLKO Rise Time
—
15
30
ns
13
T
CK
F
CLKO Fall Time
—
15
30
ns
14
T
CK
L2
IO
V CLKO
to Port Out Valid
—
—
0.5 T
CY
+ 20
ns
15
T
IO
V2
CK
H Port In Valid before CLKO
0.25
T
CY
+ 25
—
—
ns
16
T
CK
H2
IO
I
Port In Hold after CLKO
0
—
—
ns
17
T
OS
H2
IO
V OSC1
(Q1 cycle) to Port Out Valid
—
50
150
ns
18
T
OS
H2
IO
I OSC1
(Q2 cycle) to Port Input Invalid
(I/O in hold time)
100
—
—
ns
19
T
IO
V2
OS
H Port Input Valid to OSC1
(I/O in setup time)
0
—
—
ns
20
T
IO
R
Port Output Rise Time
—
10
25
ns
21
T
IO
F
Port Output Fall Time
—
10
25
ns
22
T
INP
INTx pin High or Low Time
20
—
—
ns
23
T
RBP
RB<7:4> Change INTx High or Low
Time
Time
T
CY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1:
Measurements are taken in EC mode, where CLKO output is 4 x T
OSC
.
Note:
Refer to
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2
Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value