Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet

 2009-2011 Microchip Technology Inc.

DS39960D-page 75

The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.

A Power-on Reset condition is generated on-chip
whenever V

DD

 rises above a certain threshold. This

allows the device to start in the initialized state when
V

DD

 is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k

 to 10 k) to V

DD

. This will

eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V

DD

 is specified (Parameter D004). For a slow rise

time, see 

When the device starts normal operation (exiting the
Reset condition), device operating parameters (such
as voltage, frequency and temperature) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs and does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset. 

The PIC18F87K22 family has four BOR Power modes:
• High-Power BOR
• Medium Power BOR
• Low-Power BOR
• Zero-Power BOR
Each power Mode is selected by the BORPWR<1:0>
bits setting (CONFIG2L<6:5>). For low, medium and
high-power BOR, the module monitors the V

DD

 depend-

ing on the BORV<1:0> setting (CONFIG1L<3:2>). A
BOR event re-arms the Power-on Reset. It also causes
a Reset, depending on which of the trip levels has been
set: 1.8V, 2V, 2.7V or 3V.
BOR is enabled by the BOREN<1:0> bits
(CONFIG2L<2:1>) and the SBOREN bit (RCON<6>).
Typical power consumption is listed as Parameter

In Zero-Power BOR (ZPBORMV), the module monitors
the V

DD

 voltage and re-arms the POR at about 2V.

ZPBORMV does not cause a Reset, but re-arms the
POR.
The BOR accuracy varies with its power level. The lower
the power setting, the less accurate the BOR trip levels
are. Therefore, the high-power BOR has the highest
accuracy and the low-power BOR has the lowest
accuracy. The trip levels (BV

DD

, Parameter D005), cur-

rent consumption (

) and time required

below BV

DD

 (T

BOR

, Parameter 35) can all be found in

5.4.1

DETECTING BOR

The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
LP-BOR cannot be detected with the BOR bit in the
RCON register. LP-BOR can rearm the POR and can
cause a Power-on Reset.

External Power-on Reset circuit is required
only if the V

DD

 power-up slope is too slow.

The diode, D, helps discharge the capacitor
quickly when V

DD

 powers down.

R < 40 k

 is recommended to make sure that

the voltage drop across R does not violate
the device’s electrical specification.

R1 

 1 k will limit any current flowing into

MCLR from external capacitor, C, in the event
of MCLR/V

PP

 pin breakdown due to

Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).

C

R1

R

D

V

DD

MCLR

V

DD