Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 138
© 2009 Microchip Technology Inc.
TABLE 11-11: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/RD/
P2D
P2D
RE0
0
O
DIG
LATE<0> data output.
1
I
ST
PORTE<0> data input.
AD8
(3)
x
O
DIG
External memory interface, address/data bit 8 output.
(2)
x
I
TTL
External memory interface, data bit 8 input.
(2)
RD
1
I
TTL
Parallel Slave Port read enable control input.
P2D
0
O
DIG
ECCP2 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/WR/
P2C
P2C
RE1
0
O
DIG
LATE<1> data output.
1
I
ST
PORTE<1> data input.
AD9
(3)
x
O
DIG
External memory interface, address/data bit 9 output.
(2)
x
I
TTL
External memory interface, data bit 9 input.
(2)
WR
1
I
TTL
Parallel Slave Port write enable control input.
P2C
0
O
DIG
ECCP2 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/CS/
P2B
P2B
RE2
0
O
DIG
LATE<2> data output.
1
I
ST
PORTE<2> data input.
AD10
(3)
x
O
DIG
External memory interface, address/data bit 10 output.
(2)
x
I
TTL
External memory interface, data bit 10 input.
(2)
CS
1
I
TTL
Parallel Slave Port chip select control input.
P2B
0
O
DIG
ECCP2 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
P3C
P3C
RE3
0
O
DIG
LATE<3> data output.
1
I
ST
PORTE<3> data input.
AD11
(3)
x
O
DIG
External memory interface, address/data bit 11 output.
(2)
x
I
TTL
External memory interface, data bit 11 input.
(2)
P3C
(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE4/AD12/
P3B
P3B
RE4
0
O
DIG
LATE<4> data output.
1
I
ST
PORTE<4> data input.
AD12
(3)
x
O
DIG
External memory interface, address/data bit 12 output.
(2)
x
I
TTL
External memory interface, data bit 12 input.
(2)
P3B
(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE5/AD13/
P1C
P1C
RE5
0
O
DIG
LATE<5> data output.
1
I
ST
PORTE<5> data input.
AD13
(3)
x
O
DIG
External memory interface, address/data bit 13 output.
(2)
x
I
TTL
External memory interface, data bit 13 input.
(2)
P1C
(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1:
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2:
External memory interface I/O takes priority over all other digital and PSP I/O.
3:
Available on 80-pin devices only.
4:
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).