Data Sheet (PIC18F65J15-I/PT)Table of ContentsSpecial Microcontroller Features:3Flexible Oscillator Structure:3Peripheral Highlights:3External Memory Bus (PIC18F8XJ10/8XJ15 only):3Pin Diagrams4Pin Diagrams (Continued)5Table of Contents6Most Current Data Sheet6Errata6Customer Notification System61.0 Device Overview71.1 Core Features71.1.1 nanoWatt Technology71.1.2 Oscillator Options and Features71.1.3 Expanded Memory71.1.4 External Memory Bus71.1.5 Extended Instruction Set71.1.6 Easy Migration81.2 Other Special Features81.3 Details on Individual Family Members8TABLE 1-1: Device Features for the PIC18F87J10 Family (64-pin Devices)9TABLE 1-2: Device Features for the PIC18F87J10 Family (80-pin Devices)9FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-pin) Block Diagram10FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-pin) Block Diagram11TABLE 1-3: PIC18F6XJ10/6XJ15 Pinout I/O Descriptions12TABLE 1-4: PIC18F8XJ10/8XJ15 Pinout I/O Descriptions192.0 Guidelines for Getting Started with PIC18FJ Microcontrollers292.1 Basic Connection Requirements29FIGURE 2-1: Recommended Minimum connections292.2 Power Supply Pins302.2.1 Decoupling Capacitors302.2.2 Tank Capacitors302.3 Master Clear (MCLR) Pin30FIGURE 2-2: Example of MCLR Pin Connections302.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)31FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap312.5 ICSP Pins312.6 External Oscillator Pins32FIGURE 2-4: Suggested Placement of the Oscillator Circuit322.7 Unused I/Os323.0 Oscillator Configurations333.1 Oscillator Types333.2 Crystal Oscillator/Ceramic Resonators (HS Modes)33FIGURE 3-1: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)33TABLE 3-1: Capacitor Selection for Ceramic Resonators33TABLE 3-2: Capacitor Selection for Crystal Oscillator343.3 External Clock Input (EC Modes)34FIGURE 3-2: External Clock Input Operation (EC Configuration)34FIGURE 3-3: External Clock Input Operation (HS OSC Configuration)343.4 PLL Frequency Multiplier35FIGURE 3-4: PLL Block Diagram35Register 3-1: OSCTUNE: PLL Control Register353.5 Internal Oscillator Block363.6 Clock Sources and Oscillator Switching36FIGURE 3-5: PIC18F87J10 Family Clock Diagram363.6.1 Oscillator Control Register373.6.2 Oscillator Transitions37Register 3-2: OSCCON: Oscillator Control Register383.7 Effects of Power-Managed Modes on the Various Clock Sources393.8 Power-up Delays39TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode394.0 Power-Managed Modes414.1 Selecting Power-Managed Modes414.1.1 Clock Sources414.1.2 Entering Power-Managed Modes41TABLE 4-1: Power-Managed Modes414.1.3 Clock Transitions and Status Indicators424.1.4 Multiple Sleep Commands424.2 Run Modes424.2.1 PRI_RUN Mode424.2.2 SEC_RUN Mode42FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode43FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)434.2.3 RC_RUN Mode44FIGURE 4-3: Transition Timing to RC_RUN Mode44FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode444.3 Sleep Mode454.4 Idle Modes45FIGURE 4-5: Transition Timing for Entry to Sleep Mode45FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)454.4.1 PRI_IDLE Mode464.4.2 SEC_IDLE Mode46FIGURE 4-7: Transition Timing for Entry to Idle Mode46FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode464.4.3 RC_IDLE Mode474.5 Exiting Idle and Sleep Modes474.5.1 Exit By Interrupt474.5.2 Exit By WDT Time-out474.5.3 Exit By Reset474.5.4 Exit Without an Oscillator Start-up Delay475.0 Reset495.1 RCON Register49FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit49Register 5-1: RCON: Reset Control Register505.2 Master Clear (MCLR)515.3 Power-on Reset (POR)515.4 Brown-out Reset (BOR)51FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)515.4.1 Detecting BOR515.5 Power-up Timer (PWRT)525.5.1 Time-out Sequence52FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)52FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 152FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 253FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)535.6 Reset State of Registers54TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register54TABLE 5-2: Initialization Conditions for All Registers556.0 Memory Organization616.1 Program Memory Organization61FIGURE 6-1: Memory Maps for PIC18F87J10 Family Devices616.1.1 Hard Memory Vectors62FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F87J10 Family Devices626.1.2 Flash Configuration Words62TABLE 6-1: Flash Configuration Word for PIC18F87J10 Family Devices626.1.3 PIC18F8XJ10/8XJ15 Program Memory Modes63Register 6-1: CONFIG3L: Configuration Register 3 lOw636.1.4 Extended Microcontroller Mode and Address Shifting64FIGURE 6-3: Memory Maps for PIC18F87J10 Family Program Memory Modes64TABLE 6-2: Memory Access for PIC18F8XJ10/8XJ15 Program Memory Modes646.1.5 Program Counter656.1.6 Return Address Stack65FIGURE 6-4: Return Address Stack and Associated Registers65Register 6-2: STKPTR: Stack Pointer Register666.1.7 Fast Register Stack67EXAMPLE 6-1: Fast Register Stack Code Example676.1.8 Look-up Tables in Program Memory67EXAMPLE 6-2: Computed GOTO Using an Offset Value676.2 PIC18 Instruction Cycle686.2.1 Clocking Scheme686.2.2 Instruction Flow/Pipelining68FIGURE 6-5: Clock/ Instruction Cycle68EXAMPLE 6-3: Instruction Pipeline Flow686.2.3 Instructions in Program Memory69FIGURE 6-6: Instructions in Program Memory696.2.4 Two-Word Instructions69EXAMPLE 6-4: Two-Word Instructions696.3 Data Memory Organization706.3.1 Bank Select Register70FIGURE 6-7: Data Memory Map for PIC18FX5J10/X5J15/X6J10 Devices71FIGURE 6-8: Data Memory Map for PIC18FX6J15/X7J10 Devices72FIGURE 6-9: Use of the Bank Select Register (Direct Addressing)736.3.2 Access Bank736.3.3 General Purpose Register File736.3.4 Special Function Registers74TABLE 6-3: Special Function Register Map for PIC18F87J10 Family Devices74TABLE 6-4: Register File Summary (PIC18F87J10 Family)756.3.5 STATUS Register79Register 6-3: Status Register796.4 Data Addressing Modes806.4.1 Inherent and Literal Addressing806.4.2 Direct Addressing806.4.3 Indirect Addressing80EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing80FIGURE 6-10: Indirect Addressing816.5 Program Memory and the Extended Instruction Set836.6 Data Memory and the Extended Instruction Set836.6.1 Indexed Addressing with Literal Offset836.6.2 Instructions Affected By Indexed Literal Offset Mode83FIGURE 6-11: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)846.6.3 Mapping the Access Bank in Indexed Literal Offset Mode856.6.4 BSR in Indexed Literal Offset Mode85FIGURE 6-12: Remapping the Access Bank with Indexed Literal Offset Addressing857.0 Flash Program Memory877.1 Table Reads and Table Writes87FIGURE 7-1: Table Read Operation87FIGURE 7-2: Table Write Operation887.2 Control Registers887.2.1 EECON1 and EECON2 Registers88Register 7-1: EECON1: EEPROM Control Register 1897.2.2 Table Latch Register (TABLAT)907.2.3 Table Pointer Register (TBLPTR)907.2.4 Table Pointer Boundaries90TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions90FIGURE 7-3: Table Pointer Boundaries Based on Operation907.3 Reading the Flash Program Memory91FIGURE 7-4: Reads from Flash Program Memory91EXAMPLE 7-1: Reading a Flash Program Memory Word917.4 Erasing Flash Program Memory927.4.1 Flash Program Memory Erase Sequence92EXAMPLE 7-2: Erasing Flash Program Memory927.5 Writing to Flash Program Memory93FIGURE 7-5: Table Writes to Flash Program Memory937.5.1 Flash Program Memory Write Sequence93EXAMPLE 7-3: Writing to Flash Program Memory947.5.2 Write Verify957.5.3 Unexpected Termination of Write Operation957.6 Flash Program Operation During Code Protection95TABLE 7-2: Registers Associated with Program Flash Memory958.0 External Memory Bus97TABLE 8-1: PIC18F8XJ10/8XJ15 External Bus – I/O Port Functions978.1 External Memory Bus Control98Register 8-1: MEMCON: External Memory Bus Control Register988.2 Address and Data Width998.2.1 Address Shifting on the External Bus998.2.2 21-bit Addressing99TABLE 8-2: Address and Data Lines for Different Address and Data Widths998.3 Wait States1008.4 Port Pin Weak Pull-ups1008.5 Program Memory Modes and the External Memory Bus1008.6 16-Bit Data Width Modes1008.6.1 16-Bit Byte Write Mode101FIGURE 8-1: 16-Bit Byte Write Mode Example1018.6.2 16-Bit Word Write Mode102FIGURE 8-2: 16-Bit Word Write Mode Example1028.6.3 16-Bit Byte Select Mode103FIGURE 8-3: 16-Bit Byte Select Mode Example1038.6.4 16-Bit Mode Timing104FIGURE 8-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)104FIGURE 8-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)1048.7 8-Bit Mode105FIGURE 8-6: 8-Bit Multiplexed Mode Example1058.7.1 8-Bit Mode Timing106FIGURE 8-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)106FIGURE 8-8: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)1068.8 Operation in Power-Managed Modes1079.0 8 X 8 Hardware Multiplier1099.1 Introduction1099.2 Operation109EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine109EXAMPLE 9-2: 8 x 8 Signed Multiply Routine109TABLE 9-1: Performance Comparison for Various Multiply Operations109EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm110EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine110EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm110EXAMPLE 9-4: 16 x 16 Signed Multiply Routine11010.0 Interrupts111FIGURE 10-1: PIC18F87J10 family Interrupt Logic11210.1 INTCON Registers113Register 10-1: INTCON: Interrupt Control Register113Register 10-2: INTCON2: Interrupt Control Register 2114Register 10-3: INTCON3: Interrupt Control Register 311510.2 PIR Registers116Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1116Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2117Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 311810.3 PIE Registers119Register 10-7: PIE1: Peripheral Interrupt Enable Register 1119Register 10-8: PIE2: Peripheral Interrupt Enable Register 2120Register 10-9: PIE3: Peripheral Interrupt Enable Register 312110.4 IPR Registers122Register 10-10: IPR1: Peripheral Interrupt Priority Register 1122Register 10-11: IPR2: Peripheral Interrupt Priority Register 2123Register 10-12: IPR3: Peripheral Interrupt Priority Register 312410.5 RCON Register125Register 10-13: RCON: Reset Control Register12510.6 INTx Pin Interrupts12610.7 TMR0 Interrupt12610.8 PORTB Interrupt-on-Change12610.9 Context Saving During Interrupts126EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM12611.0 I/O Ports127FIGURE 11-1: Generic I/O Port Operation12711.1 I/O Port Pin Capabilities12711.1.1 Pin Output Drive127TABLE 11-1: Output Drive Levels12711.1.2 Input Pins and Voltage Considerations128TABLE 11-2: Input Voltage Levels12811.2 PORTA, TRISA and LATA Registers128EXAMPLE 11-1: Initializing PORTA128TABLE 11-3: PORTA Functions129TABLE 11-4: Summary of Registers Associated with PORTA12911.3 PORTB, TRISB and LATB Registers130EXAMPLE 11-2: Initializing PORTB130TABLE 11-5: PORTB Functions131TABLE 11-6: Summary of Registers Associated with PORTB13211.4 PORTC, TRISC and LATC Registers133EXAMPLE 11-3: Initializing PORTC133TABLE 11-7: PORTC Functions134TABLE 11-8: Summary of Registers Associated with PORTC13511.5 PORTD, TRISD and LATD Registers136EXAMPLE 11-4: Initializing PORTD136TABLE 11-9: PORTD Functions137TABLE 11-10: Summary of Registers Associated with PORTD13811.6 PORTE, TRISE and LATE Registers139EXAMPLE 11-5: Initializing PORTE139TABLE 11-11: PORTE Functions140TABLE 11-12: Summary of Registers Associated with PORTE14111.7 PORTF, LATF and TRISF Registers142EXAMPLE 11-6: Initializing PORTF142TABLE 11-13: PORTF Functions143TABLE 11-14: Summary of Registers Associated with PORTF14311.8 PORTG, TRISG and LATG Registers144EXAMPLE 11-7: Initializing PORTG144TABLE 11-15: PORTG Functions145TABLE 11-16: Summary of Registers Associated with PORTG14511.9 PORTH, LATH and TRISH Registers146EXAMPLE 11-8: Initializing PORTH146TABLE 11-17: PORTH Functions147TABLE 11-18: Summary of Registers Associated with PORTH14711.10 PORTJ, TRISJ and LATJ Registers148EXAMPLE 11-9: Initializing PORTJ148TABLE 11-19: PORTJ Functions149TABLE 11-20: Summary of Registers Associated with PORTJ14911.11 Parallel Slave Port150FIGURE 11-2: PORTD and PORTE Block Diagram (Parallel Slave Port)150Register 11-1: PSPCON: Parallel Slave Port Control Register151FIGURE 11-3: Parallel Slave Port Write Waveforms151FIGURE 11-4: Parallel Slave Port Read Waveforms152TABLE 11-21: Registers Associated with Parallel Slave Port15212.0 Timer0 Module153Register 12-1: T0CON: Timer0 Control Register15312.1 Timer0 Operation15412.2 Timer0 Reads and Writes in 16-Bit Mode154FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)154FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)15412.3 Prescaler15512.3.1 Switching Prescaler Assignment15512.4 Timer0 Interrupt155TABLE 12-1: Registers Associated with Timer015513.0 Timer1 Module157Register 13-1: T1CON: Timer1 Control Register15713.1 Timer1 Operation158FIGURE 13-1: Timer1 Block Diagram158FIGURE 13-2: Timer1 Block Diagram (16-bit Read/Write Mode)15813.2 Timer1 16-Bit Read/Write Mode15913.3 Timer1 Oscillator159FIGURE 13-3: External Components for the Timer1 LP Oscillator159TABLE 13-1: Capacitor Selection for the Timer Oscillator(2,3,4)15913.3.1 Using Timer1 as a Clock Source15913.3.2 Low-Power Timer1 Option15913.3.3 Timer1 Oscillator Layout Considerations160FIGURE 13-4: Oscillator Circuit with Grounded Guard Ring16013.4 Timer1 Interrupt16013.5 Resetting Timer1 Using the ECCP Special Event Trigger16013.6 Using Timer1 as a Real-Time Clock160EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service161TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter16114.0 Timer2 Module16314.1 Timer2 Operation163Register 14-1: T2CON: Timer2 Control Register16314.2 Timer2 Interrupt16414.3 Timer2 Output164FIGURE 14-1: Timer2 Block Diagram164TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter16415.0 Timer3 Module165Register 15-1: T3CON: Timer3 Control Register16515.1 Timer3 Operation166FIGURE 15-1: Timer3 Block Diagram166FIGURE 15-2: Timer3 Block Diagram (16-bit Read/Write Mode)16615.2 Timer3 16-Bit Read/Write Mode16715.3 Using the Timer1 Oscillator as the Timer3 Clock Source16715.4 Timer3 Interrupt16715.5 Resetting Timer3 Using the ECCP Special Event Trigger167TABLE 15-1: Registers Associated with Timer3 as a Timer/Counter16716.0 Timer4 Module16916.1 Timer4 Operation169Register 16-1: T4CON: Timer4 Control Register16916.2 Timer4 Interrupt17016.3 Output of TMR4170FIGURE 16-1: Timer4 Block Diagram170TABLE 16-1: Registers Associated with Timer4 as a Timer/Counter17017.0 Capture/Compare/PWM (CCP) Modules171Register 17-1: CCPxCON: CCPx Control Register (CCP4 and CCP5)17117.1 CCP Module Configuration17217.1.1 CCP Modules and Timer Resources172TABLE 17-1: CCP Mode – Timer Resource17217.1.2 ECCP2 Pin Assignment172FIGURE 17-1: CCP/ECCP and Timer Interconnect Configurations17217.2 Capture Mode17317.2.1 CCP Pin Configuration17317.2.2 Timer1/Timer3 Mode Selection17317.2.3 Software Interrupt17317.2.4 CCP Prescaler173EXAMPLE 17-1: Changing Between Capture Prescalers (CCP5 Shown)173FIGURE 17-2: Capture Mode Operation Block Diagram17317.3 Compare Mode17417.3.1 CCP Pin Configuration17417.3.2 Timer1/Timer3 Mode Selection17417.3.3 Software Interrupt Mode174FIGURE 17-3: Compare Mode Operation Block Diagram174TABLE 17-2: Registers Associated with Capture, Compare, Timer1 and Timer317517.4 PWM Mode176FIGURE 17-4: Simplified PWM Block Diagram176FIGURE 17-5: PWM Output17617.4.1 PWM Period176EQUATION 17-1:17617.4.2 PWM Duty Cycle176EQUATION 17-2:176EQUATION 17-3:17717.4.3 Setup for PWM Operation177TABLE 17-3: Example PWM Frequencies and Resolutions at 40 MHz177TABLE 17-4: Registers Associated with PWM, Timer2 and Timer417818.0 Enhanced Capture/ Compare/PWM (ECCP) Module179Register 18-1: CCPxCON: Enhanced CCPx Control Register (ECCP1/ECCP2/ECCP3)17918.1 ECCP Outputs and Configuration18018.1.1 ECCP1/ECCP3 Outputs and Program Memory Mode18018.1.2 ECCP2 Outputs and Program Memory Modes18018.1.3 Use of CCP4 and CCP5 with ECCP1 and ECCP318018.1.4 ECCP Modules and Timer Resources180TABLE 18-1: Pin Configurations for ECCP1181TABLE 18-2: Pin Configurations for ECCP2181TABLE 18-3: Pin Configurations for ECCP318218.2 Capture and Compare Modes18218.2.1 Special Event Trigger18218.3 Standard PWM Mode18218.4 Enhanced PWM Mode18318.4.1 PWM Period183EQUATION 18-1:183FIGURE 18-1: Simplified Block Diagram of the Enhanced PWM Module18318.4.2 PWM Duty Cycle184EQUATION 18-2:184EQUATION 18-3:18418.4.3 PWM Output Configurations184TABLE 18-4: Example PWM Frequencies and Resolutions at 40 MHz184FIGURE 18-2: PWM Output Relationships (Active-High State)185FIGURE 18-3: PWM Output Relationships (Active-Low State)18518.4.4 Half-Bridge Mode186FIGURE 18-4: Half-Bridge PWM Output186FIGURE 18-5: Examples of Half-Bridge Output Mode Applications18618.4.5 Full-Bridge Mode187FIGURE 18-6: Full-Bridge PWM Output187FIGURE 18-7: Example of Full-Bridge Application188FIGURE 18-8: PWM Direction Change189FIGURE 18-9: PWM Direction Change at Near 100% Duty Cycle18918.4.6 Programmable Dead-Band Delay19018.4.7 Enhanced PWM Auto-Shutdown190Register 18-2: ECCPxDEL: PWM Dead-Band Delay Register190Register 18-3: ECCPxAS: Enhanced CCPx Auto-Shutdown Control Register19118.4.8 Start-up Considerations191FIGURE 18-10: PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled)192FIGURE 18-11: PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled)19218.4.9 Setup for PWM Operation19318.4.10 Effects of a Reset193TABLE 18-5: Registers Associated with ECCP Modules and Timer1 to Timer419419.0 Master Synchronous Serial Port (MSSP) Module19519.1 Master SSP (MSSP) Module Overview19519.2 Control Registers19519.3 SPI Mode195FIGURE 19-1: MSSP Block Diagram (SPI Mode)19519.3.1 Registers196Register 19-1: SSPxSTAT: MSSPx Status Register (SPI Mode)196Register 19-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)19719.3.2 Operation198EXAMPLE 19-1: Loading the SSP1BUF (SSP1SR) Register19819.3.3 Enabling SPI I/O19919.3.4 Typical Connection199FIGURE 19-2: SPI Master/Slave Connection19919.3.5 Master Mode200FIGURE 19-3: SPI Mode Waveform (Master Mode)20019.3.6 Slave Mode20119.3.7 Slave Select Synchronization201FIGURE 19-4: Slave Synchronization Waveform201FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)202FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)20219.3.8 Operation in Power-Managed Modes20319.3.9 Effects of a Reset20319.3.10 Bus Mode Compatibility203TABLE 19-1: SPI Bus Modes20319.3.11 SPI Clock Speed and Module Interactions203TABLE 19-2: Registers Associated with SPI Operation20419.4 I2C Mode205FIGURE 19-7: MSSP Block Diagram (I2C™ Mode)20519.4.1 Registers205Register 19-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)206Register 19-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)207Register 19-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)208Register 19-6: SSPxADD: MSSP1 and MSSP2 Address Register(1)21019.4.2 Operation21119.4.3 Slave Mode211EXAMPLE 19-2: Address Masking212FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)214FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)215FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)216FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)217FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)218FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)21919.4.4 Clock Stretching220FIGURE 19-14: Clock Synchronization Timing221FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Addressing)222FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Addressing)22319.4.5 General Call Address Support224FIGURE 19-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)22419.4.6 Master Mode225FIGURE 19-18: MSSP Block Diagram (I2C™ Master Mode)22519.4.7 Baud Rate227FIGURE 19-19: Baud Rate Generator Block Diagram227TABLE 19-3: I2C™ Clock Rate w/BRG227FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration22819.4.8 I2C Master Mode Start Condition Timing229FIGURE 19-21: First Start Bit Timing22919.4.9 I2C Master Mode Repeated Start Condition Timing230FIGURE 19-22: Repeated Start Condition Waveform23019.4.10 I2C Master Mode Transmission23119.4.11 I2C Master Mode Reception231FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Addressing)232FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-bit Addressing)23319.4.12 Acknowledge Sequence Timing23419.4.13 Stop Condition Timing234FIGURE 19-25: Acknowledge Sequence Waveform234FIGURE 19-26: Stop Condition Receive or Transmit Mode23419.4.14 Sleep Operation23519.4.15 Effects of a Reset23519.4.16 Multi-master Mode23519.4.17 Multi -master Communication, Bus Collision and Bus Arbitration235FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge235FIGURE 19-28: Bus Collision During Start Condition (SDAx Only)236FIGURE 19-29: Bus Collision During Start Condition (SCLx = 0)237FIGURE 19-30: BRG Reset Due to SDAx Arbitration During Start Condition237FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1)238FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2)238FIGURE 19-33: Bus Collision During a Stop Condition (Case 1)239FIGURE 19-34: Bus Collision During a Stop Condition (Case 2)239TABLE 19-4: Registers Associated with I2C™ Operation24020.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)241Register 20-1: TXSTAx: Transmit Status And Control Register242Register 20-2: RCSTAx: Receive Status And Control Register243Register 20-3: BAUDCONx: Baud Rate Control Register24420.1 Baud Rate Generator (BRG)24520.1.1 Operation in Power-Managed Modes24520.1.2 Sampling245TABLE 20-1: Baud Rate Formulas245EXAMPLE 20-1: Calculating Baud Rate Error246TABLE 20-2: Registers Associated with Baud Rate Generator246TABLE 20-3: Baud Rates for Asynchronous Modes24720.1.3 Auto-Baud Rate Detect249TABLE 20-4: BRG Counter Clock Rates249FIGURE 20-1: Automatic Baud Rate Calculation250FIGURE 20-2: BRG Overflow Sequence25020.2 EUSART Asynchronous Mode25120.2.1 EUSART Asynchronous Transmitter251FIGURE 20-3: EUSART Transmit Block Diagram251FIGURE 20-4: Asynchronous Transmission252FIGURE 20-5: Asynchronous Transmission (Back to Back)252TABLE 20-5: Registers Associated with Asynchronous Transmission25220.2.2 EUSART Asynchronous Receiver25320.2.3 Setting Up 9-bit Mode with Address Detect253FIGURE 20-6: EUSART Receive Block Diagram253FIGURE 20-7: Asynchronous Reception254TABLE 20-6: Registers Associated with Asynchronous Reception25420.2.4 Auto-Wake-up on Sync Break Character254FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation255FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep25520.2.5 Break Character Sequence25620.2.6 Receiving A Break Character256FIGURE 20-10: Send Break Character Sequence25620.3 EUSART Synchronous Master Mode25720.3.1 EUSART Synchronous Master Transmission257FIGURE 20-11: Synchronous Transmission257FIGURE 20-12: Synchronous Transmission (Through TXEN)258TABLE 20-7: Registers Associated with Synchronous Master Transmission25820.3.2 EUSART Synchronous Master Reception259FIGURE 20-13: Synchronous Reception (Master Mode, SREN)259TABLE 20-8: Registers Associated with Synchronous Master Reception25920.4 EUSART Synchronous Slave Mode26020.4.1 EUSART Synchronous Slave Transmission260TABLE 20-9: Registers Associated with Synchronous Slave Transmission26020.4.2 EUSART Synchronous Slave Reception261TABLE 20-10: Registers Associated with Synchronous Slave Reception26121.0 10-Bit Analog-to-Digital Converter (A/D) Module263Register 21-1: ADCON0: A/D Control Register 0263Register 21-2: ADCON1: A/D Control Register 1264Register 21-3: ADCON2: A/D Control Register 2265FIGURE 21-1: A/D Block Diagram266FIGURE 21-2: Analog Input Model26721.1 A/D Acquisition Requirements268EQUATION 21-1: Acquisition Time268EQUATION 21-2: A/D Minimum Charging Time268EQUATION 21-3: Calculating the Minimum Required Acquisition Time26821.2 Selecting and Configuring Automatic Acquisition Time26921.3 Selecting the A/D Conversion Clock269TABLE 21-1: Tad vs. Device Operating Frequencies26921.4 Configuring Analog Port Pins26921.5 A/D Conversions27021.6 Use of the ECCP2 Trigger270FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)270FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)27021.7 A/D Converter Calibration27121.8 Operation in Power-Managed Modes271TABLE 21-2: Summary of A/D Registers27122.0 Comparator Module273Register 22-1: CMCON: Comparator Control Register27322.1 Comparator Configuration274FIGURE 22-1: Comparator I/O Operating Modes27422.2 Comparator Operation27522.3 Comparator Reference275FIGURE 22-2: Single Comparator27522.3.1 External Reference Signal27522.3.2 Internal Reference Signal27522.4 Comparator Response Time27522.5 Comparator Outputs275FIGURE 22-3: Comparator Output Block Diagram27622.6 Comparator Interrupts27622.7 Comparator Operation During Sleep27622.8 Effects of a Reset27622.9 Analog Input Connection Considerations277FIGURE 22-4: Comparator Analog Input Model277TABLE 22-1: Registers Associated with Comparator Module27723.0 Comparator Voltage Reference Module27923.1 Configuring the Comparator Voltage Reference279Register 23-1: CVRCON: Comparator Voltage Reference Control Register279FIGURE 23-1: Comparator Voltage Reference Block Diagram28023.2 Voltage Reference Accuracy/Error28023.3 Operation During Sleep28023.4 Effects of a Reset28023.5 Connection Considerations280FIGURE 23-2: Comparator Voltage Reference Output Buffer Example281TABLE 23-1: Registers Associated with Comparator Voltage Reference28124.0 Special Features of the CPU28324.1 Configuration Bits28324.1.1 Considerations for Configuring the PIC18F87J10 family Devices283TABLE 24-1: Mapping of the Flash Configuration Words to the Configuration Registers283TABLE 24-2: Configuration Bits and Device IDs284Register 24-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)285Register 24-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)285Register 24-3: CONFIG2L: Configuration Register 2 Low (Byte AdDREss 300002h)286Register 24-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)286Register 24-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)287Register 24-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)287Register 24-7: DEVID1: Device ID Register 1 for PIC18F87J10 Family Devices288Register 24-8: DEVID2: Device ID Register 2 for PIC18F87J10 Family Devices28824.2 Watchdog Timer (WDT)28924.2.1 Control Register289FIGURE 24-1: WDT Block Diagram289Register 24-9: WDTCON: Watchdog Timer Control Register289TABLE 24-3: Summary of Watchdog Timer Registers28924.3 On-Chip Voltage Regulator29024.3.1 On-Chip Regulator and BOR29024.3.2 Power-up Requirements290FIGURE 24-2: Connections for the On-chip Regulator29024.4 Two-Speed Start-up29124.4.1 Special Considerations for Using Two-Speed Start-up291FIGURE 24-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)29124.5 Fail-Safe Clock Monitor292FIGURE 24-4: FSCM Block Diagram29224.5.1 FSCM and the Watchdog Timer29224.5.2 Exiting Fail-Safe Operation292FIGURE 24-5: FSCM Timing Diagram29324.5.3 FSCM Interrupts in Power-Managed Modes29324.5.4 POR or Wake-up From Sleep29324.6 Program Verification and Code Protection29424.6.1 Configuration Register Protection29424.7 In-Circuit Serial Programming29424.8 In-Circuit Debugger294TABLE 24-4: Debugger Resources29425.0 Instruction Set Summary29525.1 Standard Instruction Set295TABLE 25-1: Opcode Field Descriptions296FIGURE 25-1: General Format for Instructions297TABLE 25-2: PIC18F87J10 family Instruction Set29825.1.1 Standard Instruction Set30125.2 Extended Instruction Set33725.2.1 Extended Instruction Syntax337TABLE 25-3: Extensions to the PIC18 Instruction Set33725.2.2 Extended Instruction Set33825.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode34225.2.4 Considerations When Enabling the Extended Instruction Set34225.2.5 Special Considerations with Microchip MPLAB® IDE Tools34426.0 Development Support34526.1 MPLAB Integrated Development Environment Software34526.2 MPASM Assembler34626.3 MPLAB C18 and MPLAB C30 C Compilers34626.4 MPLINK Object Linker/ MPLIB Object Librarian34626.5 MPLAB ASM30 Assembler, Linker and Librarian34626.6 MPLAB SIM Software Simulator34626.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator34726.8 MPLAB REAL ICE In-Circuit Emulator System34726.9 MPLAB ICD 2 In-Circuit Debugger34726.10 MPLAB PM3 Device Programmer34726.11 PICSTART Plus Development Programmer34826.12 PICkit 2 Development Programmer34826.13 Demonstration, Development and Evaluation Boards34827.0 Electrical Characteristics349Absolute Maximum Ratings(†)349FIGURE 27-1: PIC18F87J10 family Voltage-frequency Graph, Regulator Disabled (Industrial)350FIGURE 27-2: PIC18F87J10 Family Voltage-Frequency Graph, Regulator Enabled (Industrial)35127.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial)35227.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial)35327.3 DC Characteristics: PIC18F87J10 Family (Industrial)360TABLE 27-1: Memory Programming Requirements362TABLE 27-2: Comparator Specifications363TABLE 27-3: Voltage Reference Specifications363TABLE 27-4: Internal Voltage Regulator Specifications36327.4 AC (Timing) Characteristics36427.4.1 Timing Parameter Symbology36427.4.2 Timing Conditions365TABLE 27-5: Temperature and Voltage Specifications – AC365FIGURE 27-3: Load Conditions for Device Timing Specifications36527.4.3 Timing Diagrams and Specifications366FIGURE 27-4: External Clock Timing (All Modes Except PLL)366TABLE 27-6: External Clock Timing Requirements366TABLE 27-7: PLL Clock Timing Specifications (Vdd = 2.7V to 3.6V)367TABLE 27-8: AC Characteristics: Internal RC Accuracy PIC18F87J10 family (Industrial)367FIGURE 27-5: CLKO and I/O Timing368TABLE 27-9: CLKO and I/O Timing Requirements368FIGURE 27-6: Program Memory Fetch Timing Diagram (8-Bit)369TABLE 27-7: Program Memory Fetch Timing Requirements (8-Bit)369FIGURE 27-8: Program Memory Read Timing Diagram370TABLE 27-10: CLKO and I/O Timing Requirements370FIGURE 27-9: Program Memory Write Timing Diagram371TABLE 27-11: Program Memory Write Timing Requirements371FIGURE 27-10: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing372TABLE 27-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements372FIGURE 27-11: Timer0 and Timer1 External Clock Timings373TABLE 27-13: Timer0 and Timer1 External Clock Requirements373FIGURE 27-12: Capture/Compare/PWM Timings (Including ECCP Modules)374TABLE 27-14: Capture/Compare/PWM Requirements (Including ECCP Modules)374TABLE 27-15: Parallel Slave Port Requirements374FIGURE 27-13: Example SPI Master Mode Timing (CKE = 0)375TABLE 27-16: Example SPI Mode Requirements (Master Mode, Cke = 0)375FIGURE 27-14: Example SPI Master Mode Timing (CKE = 1)376TABLE 27-17: Example SPI Mode Requirements (Master Mode, CKE = 1)376FIGURE 27-15: Example SPI Slave Mode Timing (CKE = 0)377TABLE 27-18: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)377FIGURE 27-16: Example SPI Slave Mode Timing (CKE = 1)378TABLE 27-19: Example SPI Slave Mode Requirements (CKE = 1)378FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing379TABLE 27-20: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)379FIGURE 27-18: I2C™ Bus Data Timing379TABLE 27-21: I2C™ Bus Data Requirements (Slave Mode)380FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms381TABLE 27-22: Master SSP I2C™ Bus Start/Stop Bits Requirements381FIGURE 27-20: Master SSP I2C™ Bus Data Timing381TABLE 27-23: Master SSP I2C™ Bus Data Requirements382FIGURE 27-21: EUSART Synchronous Transmission (Master/Slave) Timing383TABLE 27-24: EUSART Synchronous Transmission Requirements383FIGURE 27-22: EUSART Synchronous Receive (Master/Slave) Timing383TABLE 27-25: EUSART Synchronous Receive Requirements383TABLE 27-26: A/D Converter Characteristics: PIC18F87J10 family (Industrial)384FIGURE 27-23: A/D Conversion Timing384TABLE 27-27: A/D Conversion Requirements38528.0 Packaging Information38728.1 Package Marking Information38728.2 Package Details388Appendix A: Migration Between High-End Device Families393TABLE A-1: Notable Differences Between PIC18F8722 and PIC18F87J10 Families393Appendix B: Revision History395Revision A (December 2004)395Revision B (July 2005)395Revision C (December 2005)395Revision D (June 2006)395Revision E (June 2009)395Revision F (September 2009)395Index397The Microchip Web Site407Customer Change Notification Service407Customer Support407Reader Response408Product Identification System409Worldwide Sales and Service410Size: 6.44 MBPages: 410Language: EnglishOpen manual