Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 148
© 2009 Microchip Technology Inc.
11.11 Parallel Slave Port
PORTD can also function as an 8-bit wide Parallel
Slave Port, or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. It is asynchronously
readable and writable by the external world through RD
control input pin (RE0/RD) and WR control input pin
(RE1/WR).
Slave Port, or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. It is asynchronously
readable and writable by the external world through RD
control input pin (RE0/RD) and WR control input pin
(RE1/WR).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the PSPMODE bit enables port pin, RE0/RD, to be the
RD input, RE1/WR to be the WR input and RE2/CS to
be the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 11-3 and Figure 11-4,
respectively.
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the PSPMODE bit enables port pin, RE0/RD, to be the
RD input, RE1/WR to be the WR input and RE2/CS to
be the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is set. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 11-3 and Figure 11-4,
respectively.
FIGURE 11-2:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Note:
For 80-pin devices, the Parallel Slave Port
is available only in Microcontroller mode.
is available only in Microcontroller mode.
Data Bus
WR LATD
RDx
Q
D
CK
EN
Q
D
EN
RD PORTD
Pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to V
DD
and V
SS
.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
TRIS Latch