Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 253
PIC18F87J10 FAMILY
20.2.4.1
Special Considerations Using
Auto-Wake-up
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
end-of-character and cause data or framing errors. To
work properly, therefore, the initial character in the
transmission must be all ‘0’s. This can be 00h (8 bytes)
for standard RS-232 devices or 000h (12 bits) for LIN
bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., HS or HSPLL mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
end-of-character and cause data or framing errors. To
work properly, therefore, the initial character in the
transmission must be all ‘0’s. This can be 00h (8 bytes)
for standard RS-232 devices or 000h (12 bits) for LIN
bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., HS or HSPLL mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
20.2.4.2
Special Considerations Using
the WUE Bit
the WUE Bit
The timing of WUE and RCxIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RXx/DTx. The interrupt condition is then cleared by
reading the RCREGx register. Ordinarily, the data in
RCREGx will be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCxIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCxIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RXx/DTx. The interrupt condition is then cleared by
reading the RCREGx register. Ordinarily, the data in
RCREGx will be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCxIF flag is set should not be used as an
indicator of the integrity of the data in RCREGx. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 20-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 20-9:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
(1)
RXx/DTx Line
RCxIF
Note 1:
The EUSART remains in Idle while the WUE bit is set.
Bit set by user
Cleared due to user read of RCREGx
Auto-Cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
(2)
RXx/DTx Line
RCxIF
Cleared due to user read of RCREGx
SLEEP Command Executed
Note 1:
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
sequence should not depend on the presence of Q clocks.
2:
The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Note 1
Auto-Cleared
Bit set by user