Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 33
PIC18F87J10 FAMILY
3.4
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 3-1).
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 3-1).
FIGURE 3-4:
PLL BLOCK DIAGRAM
MU
X
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
F
IN
F
OUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
÷4
HS or EC
Mode
REGISTER 3-1:
OSCTUNE: PLL CONTROL REGISTER
U-0 R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
PLLEN
(1)
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
PLLEN: Frequency Multiplier PLL Enable bit
(1)
1 = PLL enabled
0 = PLL disabled
0 = PLL disabled
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read
as ‘0’.
as ‘0’.