Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 50
© 2009 Microchip Technology Inc.
5.5
Power-up Timer (PWRT)
PIC18F87J10 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J10 family
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F87J10 family
devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
μs = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
5.5.1
TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
, V
DD
RISE < T
PWRT
)
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
DD
): CASE 1
T
PWRT
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
T
PWRT
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET