Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 91
PIC18F87J10 FAMILY
7.5
Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
7.5.1
FLASH PROGRAM MEMORY WRITE
SEQUENCE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1.
program memory location should be:
1.
Read 1024 bytes into RAM.
2.
Update data values in RAM as necessary.
3.
Load Table Pointer register with address being
erased.
erased.
4.
Execute the erase procedure.
5.
Load Table Pointer register with address of first
byte being written, minus 1.
byte being written, minus 1.
6.
Write the 64 bytes into the holding registers with
auto-increment.
auto-increment.
7.
Set the WREN bit (EECON1<2>) to enable byte
writes.
writes.
8.
Disable interrupts.
9.
Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for T
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write for T
IW
(see parameter D133A).
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
An example of the required code is shown in
Example 7-3 on the following page.
Note 1: Unlike previous PIC devices, members of
the PIC18F87J10 family do not reset the
holding registers after a write occurs. The
holding registers must be cleared or
overwritten before a programming
sequence.
holding registers after a write occurs. The
holding registers must be cleared or
overwritten before a programming
sequence.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a block erase,
or a bulk erase of the entire memory, must
be performed.
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a block erase,
or a bulk erase of the entire memory, must
be performed.
TABLAT
TBLPTR = xxxx3F
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Write Register
TBLPTR = xxxxx2
Program Memory
Holding Register
Holding Register
Holding Register
Holding Register
8
8
8
8
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.