Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 96
© 2009 Microchip Technology Inc.
8.1
External Memory Bus Control
The operation of the interface is controlled by the
MEMCON register (Register 8-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
MEMCON register (Register 8-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 8.5 “Program Memory
Modes and the External Memory Bus”.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 8.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 8.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-Bit Data Width mode is selected.
program memory mode being used. This is discussed
in more detail in Section 8.5 “Program Memory
Modes and the External Memory Bus”.
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 8.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 8.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-Bit Data Width mode is selected.
REGISTER 8-1:
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
bit 7
bit 0
Legend:
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EBDIS: External Bus Disable bit
1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus
1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus
drivers are mapped as I/O ports
0 = External bus always enabled, I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 T
11 = Table reads and writes will wait 0 T
CY
10 = Table reads and writes will wait 1 T
CY
01 = Table reads and writes will wait 2 T
CY
00 = Table reads and writes will wait 3 T
CY
bit 3-2
Unimplemented: Read as ‘0
bit 1-0
WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate
1x = Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate