Microchip Technology DV164136 Data Sheet

 2011 Microchip Technology Inc.

DS80495E-page 3

When configured for I

2

C™ slave reception, the

MSSPx module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is
not read within a window after the SSPxIF interrupt
(PIRx<3>) has occurred.

The issue can be resolved in either of these ways:

• Prior to the I

2

C slave reception, enable the 

clock stretching feature.

This is done by setting the SEN bit
(SSPxCON2<0>).

• Each time the SSPxIF is set, read the 

SSPxBUF before the first rising clock edge of 
the next byte being received.

When Phase Lock Loop (PLL) is enabled, if the
PLL input frequency is higher than 8 MHz, there
may be problems accessing the RAM.

Limit the PLL input frequency from 4 MHz to
8 MHz. This will cause the system clock to
operate from 16 MHz to 32 MHz.

If it is necessary to run the device above
32 MHz, do not enable PLL and use the EC
mode.

If V

DDCORE

 drops below approximately 2.45V

while the on-chip core voltage regulator is
enabled, and operating in Voltage Tracking
mode, the REGSLP bit (WDTCON <7>) will be
automatically cleared. The REGSLP bit cannot
be set again by firmware until V

DDCORE

 rises

back above the 2.45V approximate threshold.

Additionally, the REGSLP bit retains its previous
state upon all Resets except POR.

None.

This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6) or (C2), respectively.

X

X

X

X

X

X

X

X

X

X