STMicroelectronics M24C64-WBN6P Memory IC M24C64-WBN6P Data Sheet



DocID16891 Rev 28

During the internal Write cycle, the device disconnects itself from the bus, and writes a copy 
of the data from its internal latches to the memory cells. The maximum Write time (t

w

) is 

shown in AC characteristics tables in 

, but the typical time 

is shorter. To make use of this, a polling sequence can be used by the bus master. 

The sequence, as shown in 



Initial condition: a Write cycle is in progress.



Step 1: the bus master issues a Start condition followed by a device select code (the 
first byte of the new instruction).



Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and 
the bus master goes back to Step 1. If the device has terminated the internal Write 
cycle, it responds with an Ack, indicating that the device is ready to receive the second 
part of the instruction (the first byte of this instruction having been sent during Step 1).

1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the 

figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling 

instruction in the figure).

Write cycle

in progress 

AI01847d

AI01847e

Next

Operation is

addressing the

memory

Start condition

Device select

with RW = 0

ACK

returned

YES

NO

YES

NO

ReStart

Stop

Data for the

Write cperation

Device select

with RW = 1

Send Address

and Receive ACK

First byte of instruction
with RW = 0 already
decoded by the device

YES

NO

StartCondition

Continue the

Write operation

Continue the

Random Read operation