STMicroelectronics M24C64-WBN6P Memory IC M24C64-WBN6P Data Sheet
Product codes
M24C64-WBN6P
DocID16891 Rev 28
M24C64-W M24C64-R M24C64-F
41
5.2 Read
operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 11. Read mode sequences
Start
Dev sel *
Byte addr
Byte addr
Start
Dev sel
Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Address
Read
Dev sel
Data out
Random
Address
Read
Address
Read
Stop
Start
Dev sel *
Data out
Sequential
Current
Read
Current
Read
Stop
Data out N
Start
Dev sel *
Byte addr
Byte addr
Sequention
Random
Read
Random
Read
Start
Dev sel *
Data out1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK