STMicroelectronics M24C64-WBN6P Memory IC M24C64-WBN6P Data Sheet

Product codes
M24C64-WBN6P
Page of 42
Signal description
M24C64-W M24C64-R M24C64-F 
DocID16891 Rev 28
2 Signal 
description
2.1 
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to 
output the data on SDA(out).
2.2 
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an 
open drain output that may be wire-OR’ed with other open drain or open collector signals on 
the bus. A pull-up resistor must be connected from Serial Data (SDA) to V
CC 
(
indicates how to calculate the value of the pull-up resistor).
2.3 
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least 
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V
CC
 
or V
SS
, as shown in 
. When not connected (left floating), these 
inputs are read as low (0).
For the 5-balls WLCSP package, the (E2,E1,E0) inputs are internally connected to (0,0,1).
Figure 5. Device select code
2.4 
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent 
write operations. Write operations are disabled to the entire memory array when Write 
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either 
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are 
acknowledged, Data bytes are not acknowledged.
Ai12806
VCC
M24xxx
VSS
Ei
VCC
M24xxx
VSS
Ei