Microchip Technology 93AA86C-I/SN Memory IC SOIC-8 93AA86C-I/SN Data Sheet
Product codes
93AA86C-I/SN
2003-2012 Microchip Technology Inc.
DS21797L-page 7
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.4
Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the Ready/
Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (T
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
The DO pin indicates the Ready/
Busy
status of the
device, if CS is brought high after a minimum of 250 ns
low (T
low (T
CSL
).
V
CC
must be
4.5V for proper operation of ERAL.
FIGURE 2-2:
ERAL TIMING
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/
a Start bit and then taking CS low will clear
the Ready/
Busy
status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1
A
N
-2
•••
A0
T
SV
T
CZ
Busy
Ready
High-Z
T
WC
High-Z
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
issuing a Start bit and then taking CS low
will clear the Ready/
Busy
status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Busy
Ready
High-Z
T
EC
High-Z