Microchip Technology 93AA86C-I/SN Memory IC SOIC-8 93AA86C-I/SN Data Sheet
Product codes
93AA86C-I/SN
2003-2012 Microchip Technology Inc.
DS21797L-page 9
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.8
Write
The WRITE instruction is followed by 8 bits (If ORG is
low or A-version devices) or 16 bits (If ORG pin is high
or B-version devices) of data which are written into the
specified address. The self-timed auto-erase and
programming cycle is initiated by the rising edge of CLK
on the last data bit.
low or A-version devices) or 16 bits (If ORG pin is high
or B-version devices) of data which are written into the
specified address. The self-timed auto-erase and
programming cycle is initiated by the rising edge of CLK
on the last data bit.
The DO pin indicates the Ready/
Busy
status of the
device, if CS is brought high after a minimum of 250 ns
low (T
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-6:
WRITE TIMING
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
signal on the PE pin prior to the rising
edge of the last data bit.
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/
Start bit and then taking CS low will clear
the Ready/
Busy
status from DO
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High-Z
High-Z
T
WC
T
CSL
T
CZ
T
SV