Microchip Technology DM164130-9 User Manual

 2012 Microchip Technology Inc.

DS41628B-page 33

All of the SFRs in 

 are in Bank 15 and do not require banking since this bank 

is covered by the Access Bank. Switching banks in the enhanced mid-range core 
requires two instructions, so this could potentially save a great number of instructions 
in the overall program. 

FFFh

TOSU

FD7h

TMR0H

FAFh

SPBRG

F87h

—

F5Fh

—

FFEh

TOSH

FD6h

TMR0L

FAEh

RCREG

F86h

—

F5Eh

—

FFDh

TOSL

FD5h

T0CON

FADh

TXREG

F85h

—

F5Dh

—

FFCh

STKPTR

FD4h

—

FACh

TXSTA

F84h

—

F5Ch

—

FFBh

PCLATU

FD3h

OSCCON

FABh

RCSTA

F83h

—

F5Bh

—

FFAh

PCLATH

FD2h

OSCCON2

FAAh

—

F82h

PORTC

F5Ah

—

FF9h

PCL

FD1h

WDTCON

FA9h

EEADR

F81h

PORTB

F59h

—

FF8h

TBLPTRU

FD0h

RCON

FA8h

EEDATA

F80h

PORTA

F58h

—

FF7h

TBLPTRH

FCFh

TMR1H

FA7h EECON2

F7Fh

ANSELH

F57h

—

FF6h

TBLPTRL

FCEh

TMR1L

FA6h

EECON1

F7Eh

ANSEL

F56h

—

FF5h

TABLAT

FCDh

T1CON

FA5h

—

F7Dh

—

F55h

—

FF4h

PRODH

FCCh

TMR2

FA4h

—

F7Ch

—

F54h

—

FF3h

PRODL

FCBh

PR2

FA3h

—

F7Bh

—

F53h

—

FF2h

INTCON

FCAh

T2CON

FA2h

IPR2

F7Ah

IOCB

FF1h

INTCON2

FC9h

SSPBUF

FA1h

PIR2

F79h

IOCA

FF0h

INTCON3

FC8h

SSPADD

FA0h

PIE2

F78h

WPUB

FEFh

INDF0

 FC7h

SSPSTAT

F9Fh

IPR1

F77h

WPUA

FEEh

POSTINC0

FC6h

SSPCON1

F9Eh

PIR1

F76h

SLRCON

FEDh POSTDEC0

FC5h

SSPCON2

F9Dh

PIE1

F75h

—

FECh

PREINC0

FC4h

ADRESH

F9Ch

—

F74h

—

FEBh

PLUSW0

FC3h

ADRESL

F9Bh

OSCTUNE

F73h

—

FEAh

FSR0H

FC2h

ADCON0

F9Ah

—

F72h

—

FE9h

FSR0L

FC1h

ADCON1

F99h

—

F71h

—

FE8h

WREG

FC0h

ADCON2

F98h

—

F70h

—

FE7h

INDF1

FBFh

CCPR1H

F97h

—

F6Fh

SSPMASK

FE6h

POSTINC1

FBEh

CCPR1L

F96h

—

F6Eh

—

FE5h POSTDEC1

FBDh

CCP1CON

F95h

—

F6Dh

CM1CON0

FE4h

PREINC1

FBCh VREFCON2

F94h

TRISC

F6Ch

CM2CON1

FE3h

PLUSW1

FBBh VREFCON1

F93h

TRISB

F6Bh

CM2CON0

FE2h

FSR1H

FBAh VREFCON0

F92h

TRISA

F6Ah

—

FE1h

FSR1L

FB9h

PSTRCON

F91h

—

F69h

SRCON1

FE0h

BSR

FB8h

BAUDCON

F90h

—

F68h

SRCON0

FDFh

INDF2

 FB7h PWM1CON

F8Fh

—

F67h

—

FDEh

POSTINC2

FB6h

ECCP1AS

F8Eh

—

F66h

—

FDDh POSTDEC2

FB5h

—

F8Dh

—

F65h

—

FDCh

PREINC2

FB4h

—

F8Ch

—

F64h

—

FDBh

PLUSW2

FB3h

TMR3H

F8Bh

LATC

F63h

—

FDAh

FSR2H

FB2h

TMR3L

F8Ah

LATB

F62h

—

FD9h

FSR2L

FB1h

T3CON

F89h

LATA

F61h

—

FD8h

STATUS

FB0h

SPBRGH

F88h

—

F60h

—

= Unimplemented data memory locations, read as ‘0’, 

This is not a physical register.

Unimplemented registers are read as ‘0’.