Microchip Technology 93AA66BT-I/OT Memory IC SOT-23-6 93AA66BT-I/OT Data Sheet

Product codes
93AA66BT-I/OT
Page of 38
 2003-2011 Microchip Technology Inc.
DS21795E-page 9
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.6
Erase/Write Disable and Enable 
(EWDS/EWEN)
The 93XX66A/B/C powers up in the Erase/Write
Disable (EWDS) state. All Programming modes must be
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or Vcc is removed from the device. 
To protect against accidental data disturbance, the
EWDS
 instruction can be used to disable all erase/write
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent of
both the EWEN and EWDS instructions.
FIGURE 2-5:
EWDS TIMING
FIGURE 2-6:
EWEN TIMING
2.7
Read
The  READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
devices) output string. The output data bits will toggle on
the rising edge of the CLK and are stable after the
specified time delay (T
PD
). Sequential read is possible
when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
FIGURE 2-7:
READ TIMING
CS
CLK
DI
1
0
0
0
0
x
•••
x
T
CSL
1
x
CS
CLK
DI
0
0
1
1
x
T
CSL
•••
CS
CLK
DI
DO
1
1
0
An
•••
A0
High-Z
0
Dx
•••
D0
Dx
•••
D0
•••
Dx
D0