Microchip Technology MA330026 Data Sheet
dsPIC33FJ32GP10X and dsPIC33FJ32MC10X
DS80548A-page 2
2012 Microchip Technology Inc.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected
Revisions
A0
SPI
Frame Sync
Pulse
Pulse
Frame sync pulse is not generated in Master mode when
FRMPOL = 0.
FRMPOL = 0.
X
SPI
Frame Sync
Pulse
Pulse
When in SPI Slave mode, with the frame sync pulse set as an
input, FRMDLY must be set to ‘0’.
input, FRMDLY must be set to ‘0’.
X
UART
TX Interrupt
A TX interrupt may occur before the data transmission is
complete.
complete.
X
UART
UARTEN
The Transmitter Write Pointer does not clear when the UART
is disabled (UARTEN = 0); it requires UTXEN to be set in
order to clear the Write Pointer.
is disabled (UARTEN = 0); it requires UTXEN to be set in
order to clear the Write Pointer.
X
CPU
div.sd
Instruction
Instruction
When using the div.sd instruction, the overflow bit is not
getting set when an overflow occurs.
getting set when an overflow occurs.
X
CPU
Interrupt
Disable
Disable
When a previous DISI instruction is active (i.e., the DISICNT
register is non-zero), and the value of the DISICNT register is
updated manually, the DISICNT register Freezes and disables
interrupts permanently.
register is non-zero), and the value of the DISICNT register is
updated manually, the DISICNT register Freezes and disables
interrupts permanently.
X
Oscillator
Clock
Switching
Switching
Clock switch does not abort when device enters Sleep mode.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.