Microchip Technology DM300023 Data Sheet
2008-2013 Microchip Technology Inc.
DS80000391B-page 3
dsPIC30F1010/202X
Output Compare
Module
In Dual Compare Match mode, the OCx
output is not reset when the OCxR and
OCxRS registers are loaded with values
having a difference of 1.
output is not reset when the OCxR and
OCxRS registers are loaded with values
having a difference of 1.
X
X
X
X
SPI Module in
Slave Select Mode
The SPI module slave select functionality
will not work correctly.
will not work correctly.
X
X
X
X
SPI Module in
Frame Master
Frame Master
Mode
The SPI module will fail to generate frame
synchronization pulses in Frame Master
mode if FRMDLY = 1.
synchronization pulses in Frame Master
mode if FRMDLY = 1.
X
X
X
X
SPI Module
The SMP bit does not have any effect
when the SPI module is configured for a
1:1 prescale factor in Master mode.
when the SPI module is configured for a
1:1 prescale factor in Master mode.
X
X
X
X
UART Module
If the Baud Rate Generator (BRG) register
contains an odd value and the parity
option is enabled, the module may falsely
indicate parity errors.
contains an odd value and the parity
option is enabled, the module may falsely
indicate parity errors.
X
X
X
X
UART Module
The Receive Buffer Overrun Error Status
bit (OERR) may be set prematurely.
bit (OERR) may be set prematurely.
X
X
X
X
UART Module
UART receptions may be corrupted in
High Baud Rate mode (BRGH = 1).
High Baud Rate mode (BRGH = 1).
X
X
X
X
UART Module
The UTXISEL0 bit in the U1STA register
is always read as zero regardless of the
value written to it.
is always read as zero regardless of the
value written to it.
X
X
X
X
UART Module
The auto-baud feature does not work
properly in High Baud Rate mode
(BRGH = 1).
properly in High Baud Rate mode
(BRGH = 1).
X
X
X
X
UART Module
When the auto-baud feature is enabled,
the Sync Break character (0x55) may be
loaded into the FIFO as data.
the Sync Break character (0x55) may be
loaded into the FIFO as data.
X
X
X
X
UART Module
(IrDA
®
Reception)
The operation of the RXINV bit in the
U1MODE register is inverted.
U1MODE register is inverted.
X
X
X
X
UART Module
The auto-baud feature measures baud
rate inaccurately for certain baud rate and
clock speed combinations.
rate inaccurately for certain baud rate and
clock speed combinations.
X
X
X
X
Bus Collision
The Bus Collision Status bit (BCL) does
not get set when a bus collision occurs
during a Restart or Stop event.
not get set when a bus collision occurs
during a Restart or Stop event.
X
X
X
X
10-Bit Addressing
Mode
The I2CTRN register can be written to
even if a write collision is detected.
even if a write collision is detected.
X
X
X
X
10-Bit
Addressing Mode
The ACKSTAT bit does not reflect the
status of a transmission received from an
I
status of a transmission received from an
I
2
C™ slave device.
X
X
X
X
10-Bit
Addressing Mode
The D_A status bit in the I2CSTAT register
does not get set on a write to the I2CTRN
register by an I
does not get set on a write to the I2CTRN
register by an I
2
C slave device.
X
X
X
X
TABLE 2:
SILICON ISSUE SUMMARY (CONTINUED)
Module
Feature
Item
Number
Issue Summary
Affected Revisions
(
1
)
A0
A1
A2
A3
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.