Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Data Sheet

Product codes
DM240013-2
Page of 338
 2013 Microchip Technology Inc.
 
DS30003030B-page 183
PIC24FV16KM204 FAMILY
16.2.4
RTCC CONTROL REGISTERS 
 
REGISTER 16-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
R/W-0
U-0
R/W-0
R-0, HSC
R-0, HSC
R/W-0
R/W-0
R/W-0
RTCEN
)
RTCWREN
RTCSYNC
HALFSEC
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RTCEN:
 RTCC Enable bit
1
 = RTCC module is enabled
0
 = RTCC module is disabled
bit 14
Unimplemented:
 Read as ‘0’
bit 13
RTCWREN:
 RTCC Value Registers Write Enable bit 
1
 = RTCVALH and RTCVALL registers can be written to by the user
0
 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC:
 RTCC Value Registers Read Synchronization bit
1
 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0
 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
HALFSEC:
 Half Second Status bit
(
1
 = Second half period of a second
0
 = First half period of a second
bit 10
RTCOE:
 RTCC Output Enable bit
1
 = RTCC output is enabled
0
 = RTCC output is disabled
bit 9-8
RTCPTR<1:0>:
 RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00
 = MINUTES
01
 = WEEKDAY
10
 = MONTH
11
 = Reserved
RTCVAL<7:0>:
00
 = SECONDS
01
 = HOURS
10
 = DAY
11
 = YEAR
Note 1:
The RCFGCAL register is only affected by a POR.
2:
A write to the RTCEN bit is only allowed when RTCWREN = 1.
3:
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.