Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Data Sheet
Product codes
DM240013-2
2013 Microchip Technology Inc.
DS30003030B-page 291
PIC24FV16KM204 FAMILY
TABLE 27-34: I
2
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock High Time
100 kHz mode
4.0
—
s
Must operate at a minimum of
1.5 MHz
1.5 MHz
400 kHz mode
0.6
—
s
Must operate at a minimum of
10 MHz
10 MHz
MSSPx module
1.5 T
CY
—
—
101
T
LOW
Clock Low Time
100 kHz mode
4.7
—
s
Must operate at a minimum of
1.5 MHz
1.5 MHz
400 kHz mode
1.3
—
s
Must operate at a minimum of
10 MHz
10 MHz
MSSPx module
1.5 T
CY
—
—
102
T
R
SDAx and SCLx Rise Time 100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 C
B
300
ns
C
B
is specified to be from
10 to 400 pF
103
T
F
SDAx and SCLx Fall Time 100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 C
B
300
ns
C
B
is specified to be from
10 to 400 pF
90
T
SU
:
STA
Start Condition Setup Time 100 kHz mode
4.7
—
s
Only relevant for Repeated
Start condition
Start condition
400 kHz mode
0.6
—
s
91
T
HD
:
STA
Start Condition Hold Time 100 kHz mode
4.0
—
s
After this period, the first clock
pulse is generated
pulse is generated
400 kHz mode
0.6
—
s
106
T
HD
:
DAT
Data Input Hold Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107
T
SU
:
DAT
Data Input Setup Time
100 kHz mode
250
—
ns
)
400 kHz mode
100
—
ns
92
T
SU
:
STO
Stop Condition Setup Time 100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
109
T
AA
Output Valid from Clock
100 kHz mode
—
3500
ns
)
400 kHz mode
—
—
ns
110
T
BUF
Bus Free Time
100 kHz mode
4.7
—
s
Time the bus must be free before
a new transmission can start
a new transmission can start
400 kHz mode
1.3
—
s
D102
C
B
Bus Capacitive Loading
—
400
pF
Note
1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode I
2
C™ bus device can be used in a Standard mode I
2
C bus system, but the requirement, T
SU
:
DAT
250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If
such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
T
such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
T
R
max. + T
SU
:
DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification), before the SCLx line
is released.