Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Data Sheet
Product codes
DM240013-2
2013 Microchip Technology Inc.
DS30003030B-page 75
PIC24FV16KM204 FAMILY
6.3
NVM Address Register
As with Flash program memory, the NVM Address
registers, NVMADRU and NVMADR, form the 24-bit
Effective Address (EA) of the selected row or word for
data EEPROM operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. These registers are not mapped into the
Special Function Register (SFR) space; instead, they
directly capture the EA<23:0> of the last Table Write
instruction that has been executed and select the data
EEPROM row to erase.
registers, NVMADRU and NVMADR, form the 24-bit
Effective Address (EA) of the selected row or word for
data EEPROM operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. These registers are not mapped into the
Special Function Register (SFR) space; instead, they
directly capture the EA<23:0> of the last Table Write
instruction that has been executed and select the data
EEPROM row to erase.
depicts the program
memory EA that is formed for programming and erase
operations.
Like program memory operations, the Least Significant
bit (LSb) of NVMADR is restricted to even addresses.
This is because any given address in the data EEPROM
space consists of only the lower word of the program
memory width; the upper word, including the uppermost
“phantom byte”, are unavailable. This means that the
LSb of a data EEPROM address will always be ‘0’.
Similarly, the Most Significant bit (MSb) of NVMADRU
is always ‘0’, since all addresses lie in the user program
space.
operations.
Like program memory operations, the Least Significant
bit (LSb) of NVMADR is restricted to even addresses.
This is because any given address in the data EEPROM
space consists of only the lower word of the program
memory width; the upper word, including the uppermost
“phantom byte”, are unavailable. This means that the
LSb of a data EEPROM address will always be ‘0’.
Similarly, the Most Significant bit (MSb) of NVMADRU
is always ‘0’, since all addresses lie in the user program
space.
FIGURE 6-1:
DATA EEPROM
ADDRESSING WITH
TBLPAG AND NVM
ADDRESS REGISTERS
ADDRESSING WITH
TBLPAG AND NVM
ADDRESS REGISTERS
6.4
Data EEPROM Operations
The EEPROM block is accessed using Table Read and
Write operations, similar to those used for program
memory. The TBLWTH and TBLRDH instructions are not
required for data EEPROM operations since the
memory is only 16 bits wide (data on the lower address
is valid only). The following programming operations
can be performed on the data EEPROM:
• Erase one, four or eight words
• Bulk erase the entire data EEPROM
• Write one word
• Read one word
Write operations, similar to those used for program
memory. The TBLWTH and TBLRDH instructions are not
required for data EEPROM operations since the
memory is only 16 bits wide (data on the lower address
is valid only). The following programming operations
can be performed on the data EEPROM:
• Erase one, four or eight words
• Bulk erase the entire data EEPROM
• Write one word
• Read one word
The library procedures are used in the code examples
detailed in the following sections. General descriptions
of each process are provided for users who are not
using the XC16 compiler libraries.
detailed in the following sections. General descriptions
of each process are provided for users who are not
using the XC16 compiler libraries.
24-Bit PM Address
TBLPAG
NVMADR
W Register EA
7Fh
xxxxh
0
0
NVMADRU
Note 1:
Unexpected results will be obtained if the
user attempts to read the EEPROM while
a programming or erase operation is
underway.
user attempts to read the EEPROM while
a programming or erase operation is
underway.
2:
The XC16 C compiler includes library
procedures to automatically perform the
Table Read and Table Write operations,
manage the Table Pointer and write buf-
fers, and unlock and initiate memory
write sequences. This eliminates the
need to create assembler macros or time
critical routines in C for each application.
procedures to automatically perform the
Table Read and Table Write operations,
manage the Table Pointer and write buf-
fers, and unlock and initiate memory
write sequences. This eliminates the
need to create assembler macros or time
critical routines in C for each application.