Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Data Sheet
Product codes
DM240013-2
2013 Microchip Technology Inc.
DS30003030B-page 79
PIC24FV16KM204 FAMILY
7.0
RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• LPBOR: Low-Power BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• LPBOR: Low-Power BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in
.
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by
all other Resets.
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by
all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see
bit in the RCON register to indicate the type of Reset
(see
). A Power-on Reset will clear all bits
except for the BOR and POR bits (RCON<1:0>) which
are set. The user may set or clear any bit at any time
during code execution. The RCON bits only serve as
status bits. Setting a particular Reset status bit in
software will not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
are set. The user may set or clear any bit at any time
during code execution. The RCON bits only serve as
status bits. Setting a particular Reset status bit in
software will not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
FIGURE 7-1:
RESET SYSTEM BLOCK DIAGRAM
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Resets,
refer to the “PIC24F Family Reference
Manual”
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Resets,
refer to the “PIC24F Family Reference
Manual”
, “Reset with Programmable
Brown-out Reset”
(DS39728).
Note:
Refer to the specific peripheral or
register Reset states.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
MCLR
V
DD
V
DD
Rise
Detect
POR
Sleep or Idle
Brown-out
Reset
RESET
Instruction
WDT
Module
Glitch Filter
BOR
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
BOREN<1:0>
00
01
10
11
0
SBOREN
SLEEP
1
Configuration Mismatch
Enable Voltage Regulator
(RCON<13>)
PIC24FV16KMXXX (only)