Microchip Technology MA180025 Data Sheet
PIC18F87J90 FAMILY
DS39933D-page 134
2010 Microchip Technology Inc.
TABLE 10-16: PORTG FUNCTIONS
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/LCDBIAS0
RG0
0
O
DIG
LATG<0> data output.
1
I
ST
PORTG<0> data input.
LCDBIAS0
x
I
ANA
LCD module bias voltage input.
RG1/TX2/CK2
RG1
0
O
DIG
LATG<1> data output.
1
I
ST
PORTG<1> data input.
TX2
1
O
DIG
Synchronous serial data output (AUSART module); takes priority over
port data.
port data.
CK2
1
O
DIG
Synchronous serial data input (AUSART module); user must configure
as an input.
as an input.
1
I
ST
Synchronous serial clock input (AUSART module).
RG2/RX2/DT2/
V
V
LCAP
1
RG2
0
O
DIG
LATG<2> data output.
1
I
ST
PORTG<2> data input.
RX2
1
I
ST
Asynchronous serial receive data input (AUSART module).
DT2
1
O
DIG
Synchronous serial data output (AUSART module); takes priority over
port data.
port data.
1
I
ST
Synchronous serial data input (AUSART module); user must configure
as an input.
as an input.
V
LCAP
1
x
I
ANA
LCD charge pump capacitor input.
RG3/V
LCAP
2
RG3
0
O
DIG
LATG<3> data output.
1
I
ST
PORTG<3> data input.
V
LCAP
2
x
I
ANA
LCD charge pump capacitor input.
RG4/SEG26/
RTCC
RTCC
RG4
0
O
DIG
LATG<4> data output.
1
I
ST
PORTG<4> data input.
SEG26
x
O
ANA
LCD Segment 26 output; disables all other pin functions.
RTCC
x
O
DIG
RTCC output.
Legend:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
PORTG
RDPU
REPU
RJPU
(1)
RG4
RG3
RG2
RG1
RG0
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
TRISG
SPIOD
CCP2OD CCP1OD TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
LCDSE3
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1:
Note 1:
Unimplemented on PIC18F6XJ90 devices, read as ‘0’.