Microchip Technology MA180025 Data Sheet

DS39933D-page 180

 2010 Microchip Technology Inc.

16.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:

CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.

The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:

PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •

T

OSC

 • (TMR2 Prescale Value)

If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.

F

OSC

F

PWM

---------------









log

2

 

log

-----------------------------bits

=

PWM Resolution (max)

Timer  Prescaler  (1,  4,  16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

14

12

10

8

7

6.58