Microchip Technology MA180025 Data Sheet

DS39933D-page 94

 2010 Microchip Technology Inc.

The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased. The
TBLPTR<9:0> bits are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.

7.4.1

FLASH PROGRAM MEMORY 
ERASE SEQUENCE

The sequence of events for erasing a block of internal
program memory location is:
1.

Load Table Pointer register with address being
erased.

2.

Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation. 

3.

Disable interrupts.

4.

Write 55h to EECON2.

5.

Write 0AAh to EECON2.

6.

Set the WR bit. This will begin the erase cycle.

7.

The CPU will stall for the duration of the erase
for T

IW

 (see parameter D133B).

8.

Re-enable interrupts.

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU 

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH 

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL 

ERASE 

BSF EECON1, 

WREN

BSF 

EECON1, FREE

; enable Erase operation

BCF

INTCON, GIE

; disable interrupts

MOVLW

55h

MOVWF

EECON2 

; write 55h

MOVLW

0AAh

MOVWF

EECON2 

; write 0AAh

BSF

EECON1, WR

; start erase (CPU stall)

BSF

INTCON, GIE

; re-enable interrupts