Microchip Technology MA330019-2 Data Sheet

Page of 436
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 14
© 2007-2012 Microchip Technology Inc.
FIGURE 1-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 BLOCK DIAGRAM
 16
OSC1/CLKI
OSC2/CLKO
V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
V
CAP
IC1, 2, 7, 8
I2C1
PORTA
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
Instruction
Decode and
Control
PCH    PCL
16
Program Counter
16-bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
 16
 16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control 
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
   
     Lite
ral Dat
a
 16
 16
16
 
 16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals 
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-5
CNx
UART1, 2
OC/
PWM1-4 
DCI
Remappable
Pins
DMA
RAM
DMA
Controller
PORTC
SPI1, 2
ECAN1
DAC1
Comparator
2 Ch.
RTCC
PMP/
EPSP