Microchip Technology MA330019-2 Data Sheet

Page of 436
© 2007-2012 Microchip Technology Inc.
DS70292G-page 149
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
     
REGISTER 9-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
(2)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits
(1)
111111 = Center frequency -0.375% (7.345 MHz) 



100001 = Center frequency -11.625% (6.52 MHz) 
100000 = Center frequency -12% (6.49 MHz)
011111 = Center frequency +11.625% (8.23 MHz)
011110 = Center frequency +11.25% (8.20 MHz)


•  
000001 = Center frequency +0.375% (7.40 MHz) 
000000 = Center frequency (7.37 MHz nominal)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the 
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither 
characterized nor tested.
2: This register is reset only on a Power-on Reset (POR).