Microchip Technology MA330019-2 Data Sheet

© 2007-2012 Microchip Technology Inc.

DS70292G-page 153

The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices can manage power consumption in four
ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.

dsPIC33FJ32GP302/304,  dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices allow a wide
range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in 

.

dsPIC33FJ32GP302/304,  dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in 

Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake up.

10.2.1

SLEEP MODE 

The following occur in Sleep mode: 
• The system clock source is shut down. If an 

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a 

minimum, provided that no I/O pin is sourcing 
current.

• The Fail-Safe Clock Monitor does not operate, 

since the system clock source is disabled.

• The LPRC clock continues to run in Sleep mode if 

the WDT is enabled.

• The WDT, if enabled, is automatically cleared 

prior to entering Sleep mode. 

• Some device features or peripherals can continue 

to operate. This includes items such as the input 
change notification on the I/O ports, or peripherals 
that use an external clock input.

• Any peripheral that requires the system clock 

source for its operation is disabled.

The device wakes up from Sleep mode on any of these
events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered. 

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 9. “Watchdog Timer
and Power-Saving Modes” (DS70196)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (

www.microchip.com

).

2: Some registers and associated bits

described in this section may not be avail-
able on all devices. Refer to 

 in this data

sheet for device-specific register and bit
information.

SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.

PWRSAV #SLEEP_MODE

; Put the device into SLEEP mode

PWRSAV #IDLE_MODE

; Put the device into IDLE mode