Microchip Technology MA330019-2 Data Sheet
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 250
© 2007-2012 Microchip Technology Inc.
REGISTER 19-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI<1:0>
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm
(1)
TXLARBm
(1)
TXERRm
(1)
TXREQm
RTRENm
TXmPRI<1:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
See Definition for Bits 7-0, Controls Buffer n
bit 7
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
bit 6
TXABTm: Message Aborted bit
(1)
1 = Message was aborted
0 = Message completed transmission successfully
0 = Message completed transmission successfully
bit 5
TXLARBm: Message Lost Arbitration bit
(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERRm: Error Detected During Transmission bit
(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQm: Message Send Request bit
1 = Requests that a message be sent. The bit automatically clears when the message is successfully
1 = Requests that a message be sent. The bit automatically clears when the message is successfully
sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when the TXREQ bit is set.
Note:
The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.