Microchip Technology MA330019-2 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70292G-page 265
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 21-2:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP302,
dsPIC33FJ64GP202/802 AND dsPIC33FJ128GP202/802 DEVICES
dsPIC33FJ64GP202/802 AND dsPIC33FJ128GP202/802 DEVICES
S/H0
S/H1
AN0
AN12
AN1
V
REFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
AN9
V
REFL
CH123SB
CH123NA CH123NB
+
-
S/H2
AN1
AN4
CH123SA
AN10
V
REFL
CH123SB
CH123NA CH123NB
+
-
S/H3
AN2
AN5
CH123SA
AN11
V
REFL
CH123SB
CH123NA CH123NB
+
-
CH1
(2)
CH0
CH2
(2)
CH3
(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note
1:
V
REF
+, V
REF
- inputs can be multiplexed with other analog inputs.
2:
Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
Input Selection
ADC1BUF0
VCFG<2:0>
AV
DD
AV
SS
V
REF
-
(1)
V
REF
+
(1)
V
REFH
V
REFL
SAR ADC