Microchip Technology MA330019-2 Data Sheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

DS70292G-page 62

TABLE 4-37:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

4.5.3

MOVE AND ACCUMULATOR
INSTRUCTIONS

Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.

In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal

4.5.4

MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.

In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)

4.5.5

OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed lit-
erals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.

Addressing Mode

Description

File Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the Effective Address (EA).

The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.

Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.

The sum of Wn and Wb forms the EA.

The sum of Wn and a literal forms the EA.

Note:

For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).

Note:

Not all instructions support all the address-
ing modes given above. Individual instruc-
tions may support different subsets of
these addressing modes.

Note: