Microchip Technology MA330019-2 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70292G-page 85
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.9
Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control register (RCON<9>) is set to indicate the
configuration mismatch Reset. Refer to
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control register (RCON<9>) is set to indicate the
configuration mismatch Reset. Refer to
for more information on the configuration
mismatch Reset.
6.10
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.10.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
The upper 8 bits should be programmed with 0x3F,
which is an illegal opcode value.
6.10.2
UNINITIALIZED W REGISTER
RESET
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
6.10.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to
for more information on
Security Reset.
6.11
Using the RCON Status Bits
The user application can read the Reset Control
register (RCON) after any device Reset to determine
the cause of the reset.
register (RCON) after any device Reset to determine
the cause of the reset.
provides a summary of the reset flag bit
operation.
TABLE 6-3:
RESET FLAG BIT OPERATION
Note:
The configuration mismatch feature and
associated reset flag is not available on all
devices.
associated reset flag is not available on all
devices.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR, BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized
W register access or Security Reset
W register access or Security Reset
POR, BOR
CM (RCON<9>)
Configuration Mismatch
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET instruction
POR, BOR
WDTO (RCON<4>)
WDT time-out
PWRSAV instruction,
CLRWDT instruction, POR, BOR
CLRWDT instruction, POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note: All Reset flag bits can be set or cleared by user software.