Microchip Technology ARD00342 Data Sheet

© 2011 Microchip Technology Inc.

DS22192D-page 27

Both ADCs present in the MCP3901 include a
decimation filter that is a third-order sinc (or notch)
filter. This filter processes the multi-bit bitstream into
16 or 24-bit words (depending on the WIDTH
Configuration bit). The settling time of the filter is
3 DMCLK periods. It is recommended that unsettled
data be discarded to avoid data corruption, which can
be done easily by setting the DR_LTY bit high in the
STATUS/COM register.

The resolution achievable at the output of the sinc filter
(the output of the ADC) is dependant on the OSR and
is summarized with the following table:

For 24-Bit Output mode (WIDTH = 1), the output of the
sinc filter is padded with least significant zeros for any
resolution less than 24 bits.

For 16-Bit Output modes, the output of the sinc filter is
rounded to the closest 16-bit number in order to
conserve only 16-bit words and to minimize truncation
error.

The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz) so a proper
anti-aliasing filter must be placed at the inputs. This will
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple,
first-order RC network with a sufficiently low time
constant to generate high rejection at DMCLK
frequency. 

Where:

The Normal Mode Rejection Ratio (NMRR) or gain of
the transfer function is given by the following equation: 

or: 

where: 

 shows the sinc filter frequency response: 

   

0

0

32

17

0

1

64

20

1

0

128

23

1

1

256

24

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