Microchip Technology ARD00342 Data Sheet
MCP3901
DS22192D-page 28
© 2011 Microchip Technology Inc.
5.6
ADC Output Coding
The second-order modulator, SINC
3
filter, PGA, V
REF
and analog input structure all work together to produce
the device transfer function for the Analog-to-Digital
conversion (see
the device transfer function for the Analog-to-Digital
conversion (see
The channel data is either a 16-bit or 24-bit word,
presented in a 23-bit or 15-bit plus sign, two’s
complement format, and is MSB (left) justified.
presented in a 23-bit or 15-bit plus sign, two’s
complement format, and is MSB (left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation) in order to improve the accuracy
of the ADC data.
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation) in order to improve the accuracy
of the ADC data.
In case of positive saturation (CHn+ – CHn- > V
REF
/3),
the output is locked to 7FFFFF for 24-bit mode (7FFF
for 16-bit mode). In case of negative saturation
(CHn+ – CHn- < -V
for 16-bit mode). In case of negative saturation
(CHn+ – CHn- < -V
REF
/3), the output code is locked to
800000 for 24-bit mode (8000 for 16-bit mode).
is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC
transfer function of the SINC
3
filter (see
and
).
EQUATION 5-3:
5.6.1
ADC RESOLUTION AS A FUNCTION
OF OSR
OF OSR
The ADC resolution is a function of the OSR
(
(
). The resolution is the
same for both channels. No matter what the resolution
is, the ADC output data is always presented in 24-bit
words, with added zeros at the end if the OSR is not
large enough to produce 24-bit resolution (left
justification).
is, the ADC output data is always presented in 24-bit
words, with added zeros at the end if the OSR is not
large enough to produce 24-bit resolution (left
justification).
DATA_CHn
CH
n+
CH
n-
–
(
)
V
REF+
V
REF-
–
-------------------------------------
⎝
⎠
⎛
⎞
8,388,608
G
3
×
×
×
=
DATA_CHn
CH
n+
CH
n-
–
(
)
V
REF+
V
REF-
–
-------------------------------------
⎝
⎠
⎛
⎞
32 768
,
G
3
×
×
×
=
(For 24-Bit Mode or WIDTH = 1)
(For 16-Bit Mode or WIDTH = 0)
TABLE 5-4:
OSR = 256 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First)
Hexadecimal
Decimal
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0x7FFFFF
+ 8,388,607
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 0
0x7FFFFE
+ 8,388,606
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0x000000
0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0xFFFFFF
-1
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0x800001
- 8,388,607
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0x800000
- 8,388,608
TABLE 5-5:
OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First)
Hexadecimal
Decimal
23-Bit Resolution
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 0
0x7FFFFE
+ 4,194,303
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 0
1 1 1 1
1 1 0 0
0x7FFFFC
+ 4,194,302
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0x000000
0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 0
0xFFFFFE
-1
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 0
0x800002
- 4,194,303
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0x800000
- 4,194,304