Microchip Technology DV164136 Data Sheet

Page of 446
PIC18F8722 FAMILY
DS39646C-page 8
© 2008 Microchip Technology Inc.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust operation:
• Fail-Safe Clock Monitor: This option constantly 
monitors the main clock source against a reference 
signal provided by the internal oscillator. If a clock 
failure occurs, the controller is switched to the 
internal oscillator block, allowing for continued 
low-speed operation or a safe application shutdown.
• Two-Speed Start-up: This option allows the 
internal oscillator to serve as the clock source 
from Power-on Reset, or wake-up from Sleep 
mode, until the primary clock source is available.
1.1.4
EXTERNAL MEMORY INTERFACE
In the unlikely event that 128 Kbytes of program
memory is inadequate for an application, the
PIC18F8527/8622/8627/8722 members of the family
also implement an external memory interface. This
allows the controller’s internal program counter to
address a memory space of up to 2 Mbytes,
permitting a level of data access that few 8-bit devices
can claim. 
With the addition of new operating modes, the external
memory interface offers many new options, including:
• Operating the microcontroller entirely from 
external memory
• Using combinations of on-chip and external 
memory, up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable 
application code or large data tables
• Using external RAM devices for storing large 
amounts of variable data
1.1.5
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. 
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
1.2
Other Special Features
• Communications: The PIC18F8722 family 
incorporates a range of serial communication 
peripherals, including 2 independent Enhanced 
USARTs and 2 Master SSP modules capable of 
both SPI and I
2
C (Master and Slave) modes of 
operation. Also, one of the general purpose I/O 
ports can be reconfigured as an 8-bit Parallel 
Slave Port for direct processor-to-processor 
communications.
• CCP Modules: All devices in the family 
incorporate two Capture/Compare/PWM (CCP) 
modules and three Enhanced CCP (ECCP) 
modules to maximize flexibility in control 
applications. Up to four different time bases may 
be used to perform several different operations at 
once. Each of the three ECCP modules offer up to 
four PWM outputs, allowing for a total of 
12 PWMs. The ECCPs also offer many beneficial 
features, including polarity selection, 
Programmable Dead-Time, Auto-Shutdown and 
Restart and Half-Bridge and Full-Bridge 
Output modes.
• Self-Programmability: These devices can write 
to their own program memory spaces under 
internal software control. By using a bootloader 
routine located in the protected boot block at the 
top of program memory, it becomes possible to 
create an application that can update itself in the 
field.
• Extended Instruction Set: The PIC18F8722 
family introduces an optional extension to the 
PIC18 instruction set, which adds 8 new instruc-
tions and an Indexed Addressing mode. This 
extension, enabled as a device configuration 
option, has been specifically designed to optimize 
re-entrant application code originally developed in 
high-level languages, such as C.
• 10-bit A/D Converter: This module incorporates 
programmable acquisition time, allowing for a 
channel to be selected and a conversion to be 
initiated without waiting for a sampling period and 
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This 
enhanced version incorporates a 16-bit prescaler, 
allowing an extended time-out range that is stable 
across operating voltage and temperature. See 
Section 28.0 “Electrical Characteristics” for 
time-out periods.