Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 146
© 2008 Microchip Technology Inc.
11.5
PORTE, TRISE and
LATE Registers
LATE Registers
PORTE is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISE. Setting
a TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output
corresponding Data Direction register is TRISE. Setting
a TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the
selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the device is operating in Microcontroller mode,
pin RE7 can be configured as the alternate peripheral
pin for the ECCP2 module. This is done by clearing the
CCP2MX Configuration bit.
pin RE7 can be configured as the alternate peripheral
pin for the ECCP2 module. This is done by clearing the
CCP2MX Configuration bit.
In 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled (80-pin
devices only), PORTE is the high-order byte of the
multiplexed address/data bus (AD<15:8>). The TRISE
bits are also overridden.
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled (80-pin
devices only), PORTE is the high-order byte of the
multiplexed address/data bus (AD<15:8>). The TRISE
bits are also overridden.
When the Parallel Slave Port is active on PORTD,
three of the PORTE pins (RE0/AD8/RD/P2D,
RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are config-
ured as digital control inputs for the port. The control
functions are summarized in Table 11-9. The reconfigu-
ration occurs automatically when the PSPMODE control
bit (PSPCON<4>) is set. Users must still make certain
the corresponding TRISE bits are set to configure these
pins as digital inputs.
three of the PORTE pins (RE0/AD8/RD/P2D,
RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are config-
ured as digital control inputs for the port. The control
functions are summarized in Table 11-9. The reconfigu-
ration occurs automatically when the PSPMODE control
bit (PSPCON<4>) is set. Users must still make certain
the corresponding TRISE bits are set to configure these
pins as digital inputs.
EXAMPLE 11-5:
INITIALIZING PORTE
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
configured as digital inputs.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
03h
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE<1:0> as inputs
; RE<7:2> as outputs