Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 177
PIC18F8722 FAMILY
16.0
TIMER4 MODULE
The Timer4 timer module has the following features:
• 8-bit Timer register (TMR4)
• 8-bit Period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
• 8-bit Period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 16-1.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 16-1 is a simplified
block diagram of the Timer4 module.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 16-1 is a simplified
block diagram of the Timer4 module.
16.1
Timer4 Operation
Timer4 can be used as the PWM time base for the
PWM mode of the CCP modules. The TMR4 register is
readable and writable and is cleared on any device
Reset. The input clock (F
PWM mode of the CCP modules. The TMR4 register is
readable and writable and is cleared on any device
Reset. The input clock (F
OSC
/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS<1:0> (T4CON<1:0>). The match output of
TMR4 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR4
interrupt, latched in flag bit, TMR4IF (PIR3<3>).
T4CKPS<1:0> (T4CON<1:0>). The match output of
TMR4 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR4
interrupt, latched in flag bit, TMR4IF (PIR3<3>).
The prescaler and postscaler counters are cleared
when any of the following occurs:
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 16-1:
T4CON: TIMER4 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
T4OUTPS3
T4OUTPS2
T4OUTPS1
T4OUTPS0
TMR4ON
T4CKPS1
T4CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T4OUTPS<3:0>: Timer4 Output Postscale Select bits
0000
= 1:1 Postscale
0001
= 1:2 Postscale
•
•
•
1111
•
•
1111
= 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1
= Timer4 is on
0
= Timer4 is off
bit 1-0
T4CKPS<1:0>: Timer4 Clock Prescale Select bits
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16