Microchip Technology DV164136 Data Sheet

© 2008 Microchip Technology Inc.

DS39646C-page 181

In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:

• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge

The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in the CCPRx registers is read, the old
captured value is overwritten by the new captured value.

17.2.1

CCPx PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.        

17.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 17.1.1 “CCP Modules and Timer
Resources”).

17.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.

17.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
CCP module is turned off, or Capture mode is disabled,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.

Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 17-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.

If a CCPx pin is configured as an output, a
write to the port can cause a capture
condition. 

CLRF

CCP5CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP5CON

; Load CCP5CON with

; this value

CCPR4H

CCPR4L

TMR1H

TMR1L

Set Flag bit CCP4IF

TMR3
Enable

Q’s

CCP1CON<3:0>

RG3/CCP4 pin

Prescaler
÷ 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1
Enable

T3CCP2

T3CCP2