Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 210
© 2008 Microchip Technology Inc.
19.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCKx. The master determines
when the slave (Processor 1, Figure 19-2) is to
broadcast data by the software protocol.
because it controls the SCKx. The master determines
when the slave (Processor 1, Figure 19-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDOx output could be dis-
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx
pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPxCON1<4>). This then,
would give waveforms for SPI communication as
programming the CKP bit (SSPxCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 19-3, Figure 19-5 and Figure 19-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
OSC
/4 (or T
CY
)
• F
OSC
/16 (or 4 • T
CY
)
• F
OSC
/64 (or 16 • T
CY
)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
10.00 Mbps.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 19-3:
SPI MODE WAVEFORM (MASTER MODE)
SCKx
(CKP = 0
(CKP = 0
SCKx
(CKP = 1
(CKP = 1
SCKx
(CKP = 0
(CKP = 0
SCKx
(CKP = 1
(CKP = 1
4 Clock
Modes
Modes
Input
Sample
Sample
Input
Sample
Sample
SDIx
bit 7
bit 0
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
SDIx
SSPxIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPxBUF
SSPxBUF
SSPxSR to
SSPxBUF
SSPxBUF
SDOx
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2
after Q2
↓
bit 0