Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 219
PIC18F8722 FAMILY
19.4.2
OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPxCON1<5>).
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I
2
C
operation. Four mode selection bits (SSPxCON1<3:0>)
allow one of the following I
allow one of the following I
2
C modes to be selected:
• I
2
C Master mode, clock
• I
2
C Slave mode (7-bit address)
• I
2
C Slave mode (10-bit address)
• I
2
C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I
2
C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I
2
C Firmware Controlled Master mode, slave is
Idle
Selection of any I
2
C mode with the SSPEN bit set
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
19.4.3
SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I
2
C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I
low for proper operation. The high and low times of the
I
2
C specification, as well as the requirement of the
19.4.3.1
Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
The SSPxSR register value is loaded into the
SSPxBUF register.
SSPxBUF register.
2.
The Buffer Full bit, BF, is set.
3.
An ACK pulse is generated.
4.
The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0
’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
follows, with steps 7 through 9 for the slave-transmitter:
1.
Receive first (high) byte of address (bits SSPxIF,
BF and UA (SSPxSTAT<1>) are set on address
match).
BF and UA (SSPxSTAT<1>) are set on address
match).
2.
Update the SSPxADD register with second (low)
byte of address (clears bit UA and releases the
SCLx line).
byte of address (clears bit UA and releases the
SCLx line).
3.
Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
clear flag bit SSPxIF.
4.
Receive second (low) byte of address (bits
SSPxIF, BF and UA are set).
SSPxIF, BF and UA are set).
5.
Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
6.
Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
clear flag bit SSPxIF.
7.
Receive Repeated Start condition.
8.
Receive first (high) byte of address (bits SSPxIF
and BF are set).
and BF are set).
9.
Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
clear flag bit SSPxIF.